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PI6LC4820 Datasheet(PDF) 3 Page - Pericom Semiconductor Corporation

Part # PI6LC4820
Description  HiFlex Ethernet Network Clock Generator
PDF  13 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI6LC4820 Datasheet(HTML) 3 Page - Pericom Semiconductor Corporation

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PI6LC4820 Rev D
11/13/13
PI6LC4820
HiFlexTM Ethernet Network Clock Generator
Pin Description
Pin Number Pin Name
Type
Description
1
FS0
Input (LVCMOS)
Frequency Select Pin. Use FS0=FS1=0 for all 25MHz input sources.
Internal pull-down is 100K-Ohm
2
X1
Input
Crystal input pin. No internal xtal load capacitance
3
X2
Output
Crystal output pin. No internal xtal load capacitance
4
VDD_OSC
Power
VDD for reference oscillator
5
IN_SEL
Input (LVCMOS)
Input mux selection pin
6
PLL_BYPS
Input (LVCMOS)
Optional mode to bypass PLL and have input reference source connect
directly to outputs
7
GND
Power
Ground pin
8
FS1
Input (LVCMOS)
Frequency Select Pin. Use FS0=FS1=0 for all 25MHz input sources.
Internal pull-down is 100K-Ohm
9
QC_Mode
Input (LVCMOS)
Out mode control pin selects LVPECL or LVDS mode. If left floating,
outputs are tri-stated
10
VDDA
Power
VDD for analog circuitry
11
GND
Power
Ground pin
12
VDD_PLL
Power
VDD for PLL.
13
GND
Power
Ground pin
14
FS_B
Input (LVCMOS)
Frequency Select Pin for Bank B, Output Divider
15
GND
Power
Ground pin
16
FS_A
Input (LVCMOS)
Frequency Select Pin for Bank A, Output Divider
17
GND
Power
Ground pin
18
FS_C
Input (LVCMOS)
Frequency Select Pin for Bank C, Output Divider
19
QA_Mode1
Input (LVCMOS)
Out mode control pin selects LVPECL or LVDS mode. If left floating,
outputs are tri-stated
20
VDD
Power
VDD
21
GND
Power
Ground pin
22,
23
QC-,
QC+
Output (Differential)
Bank C LVDS/LVPECL selectable output. Controlled by QC_Mode pin
24
VDD_QC
Power
VDD for bank C outputs
25
VDD_QA
Power
VDD for bank A outputs
26,
27
QA4-,
QA4+
Output (Differential)
Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode1 pin
28,
29
QA3-,
QA3+
Output (Differential)
Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode1 pin
30,
31
QA2-,
QA2+
Output (Differential)
Bank A LVDS/LVPECL selectable output. Controlled by QA_Mode0 pin
13-0167



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