PI6LC4820 datasheet(7/13 Pages) PERICOM

7 / 13 page

PI6LC4820 Rev D

11/13/13

PI6LC4820

HiFlexTM Ethernet Network Clock Generator

LVPECL Output Characteristics

Symbol

Parameters

Condition

Min.

Typ.

Max.

Units

FOUT

Output Frequency

312.5

MHz

Trise / Tfall

Rise and Fall Time

20% to 80%, single-

ended

400

TDC

Duty Cycle

Differential

Jphase

Integrated phase jitter

12KHz-20MHz

@ 156.25MHz,

25MHz Xtal input

0.54

ps rms

TDIS

Output Disable Time

TEN

Output Enable Time

TLOCK

PLL Lock Time

VPP

Output peak-peak Voltage

Single-ended

0.6

VOH

Output High Voltage

VDD = 3.3V

VDD-1.4

VDD-0.9

VOL

Output Low Voltage

VDD = 3.3V

VDD-2.0

VDD-1.7

LVDS Output Characteristics

Symbol

Parameters

Condition

Min.

Typ.

Max.

Units

FOUT

Output Frequency

312.5

MHz

Trise / Tfall

Rise and Fall Time

20% to 80%, single-

ended

270

TDC

Duty Cycle

Differential

Jphase

Integrated phase jitter

12KHz-20MHz

@ 156.25MHz,

25MHz Xtal input

0.54

ps rms

Differential Input Characteristics

Symbol Parameters

Conditions

Min.

Typ.

Max.

Units

VIH

Input High Voltage

VDD - 0.7

VIL

Input Low Voltage

VDD - 2.0

VCM

Input Bias Voltage

VDD - 1.8 VDD / 2

RIN

Input Differential Impedence2

100

120

VIN-PP

Input Differential Swing

0.3

1.8

VPP

CIN

Differential Input Capacitance

1.5

Note:

1. 2. Differential input can be AC or DC coupled.

(Over Operating Conditions. See Fig. 1 and 2 for load conditions.)

(Over Operating Conditions See Fig. 1 and 2 for load conditions.)

13-0167

PI6LC4820 Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation

PI6LC4820 Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL