PI6LC4820 datasheet(1/13 Pages) PERICOM

Part #	PI6LC4820

Description	HiFlex Ethernet Network Clock Generator

PDF	13 Pages

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Manufacturer	PERICOM [Pericom Semiconductor Corporation]

Direct Link	http://www.pericom.com

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1

PI6LC4820 Rev D

11/13/13

HiFlexTM Ethernet Network Clock Generator

PI6LC4820

Features

Î

3.3V supply voltage

Î

Crystal input: 25 MHz

Î

Differential input: 25MHz, 156.25 MHz

Î

Output frequencies of 312.5, 156.25, 125MHz supported

Î

9 LVPECL or LVDS bank selectable outputs

Î

Low 1ps max integrated phase noise design

(12kHz to 20MHz)

Î

Optional xtal or clock input selection

Î

PLL Bypass mode for test

Î

Power supply noise rejection: -50 dBc typical @ 156.25 MHz

Î

Packaging (Pb-free & Green): 48-lead 7×7mm TQFN

Description

The PI6LC4820 is an LC VCO based low phase noise design

intended for 10GbE applications. Typical 10GbE usage assumes

a 25Mhz crystal input, while the PLL loop is used to generate

the 156.25MHz outputs. An additional buffered crystal oscilla-

tor output is provided to serve as a low noise reference for other

circuitry.

For Ethernet applications other than 10GbE, programmable

dividers allow for simultaneous output of 312.5, 156.25, and

125MHz.

Pin Configuration

1

2

10

9

8

7

6

5

4

3

20

19

18

17

16

15

14

13

36

35

27

28

29

30

31

32

33

34

41

42

43

44

45

46

47

48

VDD_QA

QA0+

QA4+

QA3-

QA3+

QA2-

QA2+

QA1-

QA1+

QA0-

FS0

X1

VDDA

QC_Mode

FS1

GND

PLL_BYPS

IN_SEL

VDD_OSC

X2

12

11

25

26

VDD_PLL

GND

24

23

22

21

37

38

39

40

VDD_QA

QA4-

GND

13-0167

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PI6LC4820 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation

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