ADC12281 datasheet(6/16 Pages) NSC

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DC and Logic Electrical Characteristics (Continued)

The following specifications apply for AGND = DGND = DGND I/O = 0V, V

A =VD =VD I/O = +5V, PD = +5V, VREF = +2.0V,

CLK = 20MHz,3VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA =TJ =TMIN to TMAX;

all other limits T

A =TJ = 25˚C (Notes 7, 8, 9).

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

Logical “0” Input Voltage

D = 4.75V

0.8

V (max)

Logical “1” Input Current

IN = 5.0V

µA

Logical “0” Input Current

IN = 0V

−10

µA

Logic Input Capacitance

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

Logical “1” Output Voltage

OUT =−1mA

V (min)

Logical “0” Output Voltage

OUT = 1.6 mA

0.4

V (max)

TRI-STATE Output Current

OUT =3Vor5V

100

OUT = 0V

−100

Output Short Circuit Source

Current

D I/O = 3V, VOUT = 0V

−29

−I

Output Short Circuit Sink Current

D I/O = 3V, VOUT =VD

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

PD = DGND (active)

100

mA (max)

PD=V

D I/O (power-down mode)

3.5

Digital Supply Current

PD = DGND (active)

3.6

mA (max)

PD=V

D I/O (power-down mode)

Total Power Consumption

PD = DGND (active)

443

530

mW (max)

PD=V

D I/O (power-down mode)

typ

AC Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, V

A =VD =VD I/O = +5V, PD = +5V, VREF = +2.0V,

CLK = 20MHz,3VP-P at 50% duty cycle, CL = 25 pF/pin. After Auto-Cal. Boldface limits apply for TA =TJ =TMIN to TMAX;

all other limits T

A =TJ = 25˚C (Notes 7, 8, 9).

Symbol

Parameter

Conditions

Typical

(Note 10)

Limits

(Note 11)

Units

(Limits)

CLK

Conversion Clock (CLOCK) Frequency

0.5

MHz (min)

MHz (max)

CONV

Conversion Latency

Clock

Cycles

Data Output Delay after Rising CLK Edge

D I/O=3V

ns (max)

D I/O=5V

Data Outputs into TRI-STATE Mode

Data Outputs Active after TRI-STATE

WCAL

Calibration Request Pulse Width

CLK

RDYC

Ready Low after CAL Request

CLK

CAL

Calibration Cycle

4000

CLK

WPD

Power-Down Pulse Width

CLK

RDYPD

Ready Low after PD Request

CLK

Power-Down Mode Exit Cycle

4000

CLK

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND I/O = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VA,VD or VD I/O), the current at that pin should be limited

to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to

two.

ADC12281 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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