ADC12281 datasheet(7/16 Pages) NSC

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AC Electrical Characteristics (Continued)

Note 4: The absolute maximum junction temperature (TJMAX) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJMAX, the

junction-to-ambient thermal resistance (

θJA), and the ambient temperature (TA), and can be calculated using the formula PD MAX=(TJMAX –TA)/θJA. In the 32-pin

TQFP,

θJA is 79˚C/W, so PD MAX = 1,582 mW at 25˚C and 949 mW at the maximum operating ambient temperature of 75˚C. Note that the power dissipation of this

device under normal operation will typically be about 125 mW (typical power dissipation + 20 mW TTL output loading). The values for maximum power dissipation

listed above will be reached only when the ADC12281 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply

voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k

Ω resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5V above VA or to 5V below GND will not damage this device, provided current

is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is 4.75V,

the full-scale input voltage must be

≤ 4.85V to ensure accurate conversions.

10102708

ESD Protection Scheme for Analog Input and Digital Output Pins

Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 9: With the test condition for VREF = +2.0V, the 12-bit LSB is 488 µV.

Note 10: Typical figures are at TA =TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing

Quality Level).

Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 12: Integral Non-Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and

zero.

Note 13: Timing specifications are tested at the TTL logic levels, VIL −0.4V for a falling edge and VIH = 2.4V for a rising edge. TRI-STATE output voltage is forced

to 1.4V.

Note 14: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), the

LM4041CIZ-ADJ (TO-92 package), or the LM4041CIM-ADJ (SO-8 package) bandgap voltage reference is recommended for this application.

Transfer Characteristics

10102709

FIGURE 1. Transfer Characteristics

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