ADC12762 datasheet(15/20 Pages) NSC

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Applications Information (Continued)

Since the current flowing through the SENSE lines is essen-

tially zero, there is negligible voltage drop across R

S and the

Ω resistor, so the voltage at the inverting input of the op

amp accurately represents the voltage at the top (or bottom)

of the ladder. The op amp drives the FORCE input and

forces the voltage at the ends of the ladder to equal the volt-

age at the op amps’s non-inverting input, plus or minus its in-

put offset voltage. For this reason op amps with low V

OS,

such as the LMC6081, should be used for this application.

When used in this configuration, the ADC12762 has less

than 4 LSBs of offset and gain error without any user adjust-

ments.

The 0.1 µF and 10 µF capacitors on the force inputs provide

high frequency decoupling of the reference ladder. The 500

Ω

force resistors isolate the op amps from this large capacitive

load. The 0.01 µF/1 k

Ω network provides zero phase shift at

high frequencies to ensure stability. Note that the positive op

amp supply voltage must be at least 2.5V above the refer-

ence voltage and that a negative op amp supply is needed to

supply the sub-zero voltage to the V

REF− (FORCE) pin. The

REF/16 output should be bypassed to analog ground with a

0.1 µF ceramic capacitor.

The reference inputs are fully differential and define the zero

to full-scale range of the input signal. They can be configured

to span up to 5V (V

REF− = 0V, VREF+ = 5V), or they can be

connected to different voltages (within the 0V to 5V limits)

when other input spans are required. The ADC12762 is

tested at V

REF− (SENSE) = 0V, VREF+ (SENSE) = 4.096V. Re-

ducing the reference voltage span to less than 4V increases

the sensitivity (reduces the LSB size) of the converter; how-

ever noise performance degrades when lower reference

voltages are used. A plot of dynamic performance vs refer-

ence voltage is given in the Typical Performance Character-

istics section.

If the converter will be used in an application where DC ac-

curacy is secondary to dynamic performance, then a simpler

reference circuit may suffice. The circuit shown in

Figure 11

will introduce several LSBs of offset and gain error, but INL,

DNL, and all dynamic specifications will be unaffected.

All bypass capacitors should be located as close to the

ADC12762 as possible to minimize noise on the reference

ladder. The V

REF/16 output should be bypassed to analog

ground with a 0.1 µF ceramic capacitor.

The LM4040 shunt voltage reference is available with a

4.096V output voltage. With initial accuracies as low as

± 0.1%, it makes an excellent reference for the ADC12762.

DS012811-33

FIGURE 10. Reference Ladder Force and Sense Inputs

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