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TAS5751M Datasheet(PDF) 39 Page - Texas Instruments |
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TAS5751M Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 70 page ![]() 39 TAS5751M www.ti.com SLASEC1A – MARCH 2016 – REVISED MARCH 2016 Product Folder Links: TAS5751M Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Register Maps (continued) SUBADDRESS REGISTER NAME NO. OF BYTES CONTENTS DEFAULT VALUE 0x63–0x69 Reserved 4 Reserved(1) 0x0000 0000 0x6A 4 0x0000 8312 0x6B Left channel PWM level meter 4 Data[31:0] 0x007F 7CED 0x6C Right channel PWM level meter 4 Data[31:0] 0x0000 0000 0x6D Reserved 8 Reserved(1) 0x0000 0000 0000 0000 0x6E–0x6F 4 0x0000 0000 0x70 ch1 inline mixer 4 u[31:26], in_mix1[25:0] 0x0080 0000 0x71 inline_AGL_en_mixer_ch1 4 u[31:26], in_mixagl_1[25:0] 0x0000 0000 0x72 ch1 right_channel mixer 4 u[31:26], right_mix1[25:0] 0x0000 0000 0x73 ch1 left_channel_mixer 4 u[31:26], left_mix_1[25:0] 0x0080 0000 0x74 ch2 inline mixer 4 u[31:26], in_mix2[25:0] 0x0080 0000 0x75 inline_AGL_en_mixer_ch2 4 u[31:26], in_mixagl_2[25:0] 0x0000 0000 0x76 ch2 left_chanel mixer 4 u[31:26], left_mix1[25:0] 0x0000 0000 0x77 ch2 right_channel_mixer 4 u[31:26], right_mix_1[25:0] 0x0080 0000 0x78–0xF7 Reserved(1) 0x0000 0000 0xF8 Update device address key 4 Dev Id Update Key[31:0] (Key = 0xF9A5A5A5) 0x0000 0054 0xF9 Update device address 4 u[31:8],New Dev Id[7:0] (New Dev Id = 0x54 for TAS5751M) 0x0000 0054 0xFA–0xFF 4 Reserved(1) 0x0000 0000 (1) Default values are in bold. (2) Only available for 44.1-kHz and 48-kHz rates (3) Rate only available for 32/44.1/48-KHz sample rates (4) Not available at 8 kHz All DAP coefficients are 3.23 format unless specified otherwise. Registers 0x3B through 0x46 should be altered only during the initialization phase. 7.7.2 Detailed Register Descriptions 7.7.2.1 Clock Control Register (0x00) The clocks and data rates are automatically determined by the TAS5751M. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. Table 5. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – Reserved 0 1 0 – – – – – Reserved 0 1 1 – – – – – fS = 44.1/48-kHz sample rate (1) 1 0 0 – – – – – fS = 16-kHz sample rate 1 0 1 – – – – – fS = 22.05/24-kHz sample rate 1 1 0 – – – – – fS = 8-kHz sample rate 1 1 1 – – – – – fS = 11.025/12-kHz sample rate – – – 0 0 0 – – MCLK frequency = 64 × fS (2) – – – 0 0 1 1 – MCLK frequency = 128 × fS (2) 0 0 0 0 1 0 0 0 MCLK frequency = 192 × fS (3) – – – 0 1 1 – – MCLK frequency = 256 × fS (1) (4) |
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