AD7770 datasheet(52/94 Pages) AD

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AD7770

Data Sheet

Rev. A | Page 52 of 94

SRC Bandwidth

The sinc3 filter architecture allows the user to select a noninteger

value as the decimation range This versatility means that the

filter notches must be adjusted dynamically: two notches at the

variable frequency, and one fixed notch to remove the PGA

chopping tone. Consequently, the traditional formula for −0.1 dB

and −3 dB bandwidth must be adjusted depending on the

selected decimation rate.

The bandwidth transfer function is not linear but can be

approximated by using a linear function.

Figure 109 and Figure 110 show the correction factor for the

−0.1 dB and −3 dB bandwidth, respectively, in high resolution.

In low power mode, the offset must be divided by 4. For

example, when the ODR = 1000 SPS in low power mode, the

−0.1 dB point is

1000

0481

≈

200

400

600

800

1000

1200

1400

1600

ODR (kHz)

0.1

5.1

10.1

15.1

20.1

25.1

30.1

y = 0.0481x + 47.36

Figure 109. −0.1 dB Correction Factor

ODR (kHz)

0.1

5.1

10.1

15.1

20.1

25.1

30.1

y = 0.2608x + 248.64

Figure 110. −3 dB Correction Factor

SRC Group Delay

The SRC group delay depends on the selected ODR and the

power mode, and is defined by the following equation:

SRC Group Delay =

ODR

SRC

where:

PM is a value that depends on the power mode, either 64 for

high resolution mode or 32 for low power mode.

SRC_N is the integer value of the programmed ODR.

ODR is the programmed output data rate.

Settling Time

The settling time is defined by the contribution of all the

internal stages, the filter delay, and the block calibration.

The filter delay is defined as 3/ODR. In some extreme cases, such

as when an external pulse is applied, this value may increase to

4/ODR.

In high resolution mode, the calibration delay is defined as 62 ×

tMCLK, with a maximum error of 2 × tMCLK. In low power mode,

the calibration delay is defined as 121 × tMCLK, with a maximum

error of 4 × tMCLK. tMCLK is the external clock period and is 488 ns

in high resolution mode (8.192 MHz) and 1.9 µs in low power

mode (4.096 MHz)

DATA OUTPUT INTERFACE

The Σ-Δ output data interface is defined by the CONVST_SAR,

FORMAT0, and FORMAT1 pins in pin control mode at power-up.

The FORMATx pins cannot be changed dynamically. Table 14

shows the available options for pin control mode. If the device

is configured in SPI control mode, the SPI_SLAVE_MODE_

EN bit enables the SPI to transmit the Σ-Δ ADC conversion

results, as shown in Table 22.

DOUT3 to DOUT0 Data Interface

Standalone Mode

In standalone mode, the AD7770 interface acts as a master.

There are three different DOUTx configurations, configurable

through the FORMATx pins in pin control mode, as shown in

Figure 111 through Figure 113, or via the DOUT_FORMAT bits,

Bits[7:6], in SPI control mode, as described in Table 36.

Figure 114, Figure 115, and Figure 116 show the expected data

outputs for different DOUTx output modes.

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