AD7770 datasheet(69/94 Pages) AD

69 / 94 page

Data Sheet

AD7770

Rev. A | Page 69 of 94

Table 62. Bit Descriptions for GENERAL_USER_CONFIG_2

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

RESERVED

Reserved.

0x0

R/W

SAR_DIAG_MODE_EN

Sets SPI to Read Back SAR Result on SDO.

0x0

R/W

[4:3]

SDO_DRIVE_STR

SDO Drive Strength.

0x1

R/W

Nominal.

Strong.

Weak.

Extra strong.

[2:1]

DOUT_DRIVE_STR

DOUTx Drive Strength.

0x0

R/W

Nominal.

Strong.

Weak.

Extra strong.

SPI_SYNC

SYNC Pulse Generated Through SPI.

0x1

R/W

This signal is AND’ed with the value on the START pin in the control module

and generates a pulse in the SYNC_IN pin.

This bit is AND’ed with the value on START pin in the control module.

GENERAL USER CONFIGURATION 3 REGISTER

Address: 0x013, Reset: 0x80, Name: GENERAL_USER_CONFIG_3

Disable deglitching of CONVST pin

11: No deglitch circuit.

10: CONVST_SAR Deglitch 1.5 MCLK.

01: Reserved.

00: Reserved.

Disables the clock qualifier check

if the user requires to use an MCLK

signal < 265kHz.

Enable to SPI slave mode to read

back ADC on SDO

[7:6] CONVST_DEGLITCH_DIS (R/W)

[0] CLK_QUAL_DIS (R/W)

[5] RESERVED

[1] RESERVED

[4] SPI_SLAVE_MODE_EN (R/W)

[3:2] RESERVED

Table 63. Bit Descriptions for GENERAL_USER_CONFIG_3

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

CONVST_DEGLITCH_DIS

Disable deglitching of CONVST_SAR pin.

0x2

R/W

Reserved.

CONVST_SAR deglitch 1.5/MCLK.

No deglitch circuit.

RESERVED

Reserved.

0x0

R/W

SPI_SLAVE_MODE_EN

Enable to SPI slave mode to read back ADC on SDO.

0x0

R/W

[3:2]

RESERVED

Reserved.

0x0

R/W

RESERVED

Reserved.

0x0

R/W

CLK_QUAL_DIS

Disables the clock qualifier check if the user requires to use an MCLK

signal <265 kHz.

0x0

R/W

AD7770 Datasheet(PDF) 69 Page - Analog Devices

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