TAS3103DBT datasheet(56/146 Pages) TI

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2−24

between recognizing the activation of pin PWRDN and entering the power down would be 4096 LRCLK periods,

assuming a volume slew rate selection (bit VSC of I2C subaddress 0xF1) of 4096 and the issuance of a volume

update immediately preceding the reading of pin PWRDN. The worst case time lag between setting PWRDN to logic

1 and entering the power down state is then:

power – down – time lag

Worst-Case +

4096

) GPIOFSCOUNT

LRCLK

)

Microprocessor-Clock

There is also a time lag between deactivating PWRDN (setting PWRDN to logic 0) and exiting the power down state.

This time lag is set by the time it takes the internal digital PLL to stabilize, and this time, in turn, is set by the master

clock frequency (MCLKI or XTALI) and the PLL output clock frequency. For a 135-MHz PLL output clock and a 24.576

MCLKI, the time lag is approximately 25

µs. For a 11.264-MHz PLL output clock and a 1.024-MHz MCLKI, the time

lag is approximately 360

µs.

Power consumption in the power-down state is approximately 12 mW.

2.7

Watchdog Timer

There is a watchdog timer in the TAS3103 that monitors the microprocessor activity. If the microprocessor ever

ceases to execute its stored program, the watchdog timer fires and resets the TAS3103. This capability was included

in the TAS3103 for factory test purposes and has little use in applications. The program structure used in the

microprocessor assures that the microprocessor always executes its stored program unless a hardware failure

occurs.

The watchdog timer is governed by the parameter GPIOFSCOUNT in subaddress 0xEF and the LSB of the 32-bit

word at subaddress 0xEB. The default value of the LSB of the 32-bit word at subaddress 0xEB is 1 and this value

disables the watchdog timer. The GPIOFSCOUNT is also used in other functions and balancing the needs of these

other functions regarding GPIOFSCOUNT with the requirements of the watchdog timer is an involved process. For

this reason, it is strongly recommended that the LSB of the 32-bit word at subaddress 0xEB remain a 1. If an

application does require use of the watchdog timer, it is requested that the user contact an application engineer in

the Digital Audio Department of Texas Instruments for details in properly using this feature.

2.8

General-Purpose I/O (GPIO) Ports

The TAS3103 has four general-purpose I/O (GPIO) ports. Figure 2−21 is a block diagram of the GPIO circuitry in the

TAS3103.

TAS3103DBT Datasheet(PDF) 56 Page - Texas Instruments