14-Bit, 600+ MSPS

D/A Converter

Preliminary Technical Data

AD9725

Rev. PrA

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FEATURES

600+ MSPS DAC update rate

16/14/12/10-bit resolution family

LVDS interface with built-in 100-termination resistors

Single data rate and double data rate capability

Excellent dynamic performance

SFDR = 63 dBc at 140 MHz

IMD = 73 dBc at 140 MHz

Differential current outputs: 2 mA to 20 mA

–40°C to +85°C temperature range operation

On-chip 1.20 V reference

Package: 80-lead thermally-enhanced TQFP

Versatile clock and data interface

APPLICATIONS

Instrumentation and test

Wideband communications systems

Point-to-point wireless

LMDS

PA linearization

High resolution displays

FUNCTIONAL BLOCK DIAGRAM

DATA

FORMATTER

DATA CLOCK

FORMATTER

DATA SYNC.

CALIBRATION

REFERENCE

SPI

CLOCK DISTRIBUTION

AND CONTROL

14-BIT

DAC

SDIO

CSB

IOUTA

IOUTB

FSADJ

REFIO

SDO/SYNC_ALRM

SCLK/SYNC_UPD

RESET

DB[13:0]+

DB[13:0]–

DATACLK_IN+

DATACLK_IN–

REXT

DATACLK_OUT+

DATACLK_OUT–

CLK+

CLK–

DDR

Figure 1

PRODUCT DESCRIPTION

The AD9725 is a 14-bit digital-to-analog converter (DAC) that

utilizes an LVDS interface to achieve conversion rates in excess

of 600 MSPS. It is in a family of pin compatible converters that

offers selection of 10-bit, 12-bit, 14-bit, and 16-bit resolution

grades. All of the devices share the same interface options, small

outline package, and pinout, providing an upward or downward

component selection path based on performance, resolution

and cost.

PRODUCT HIGHLIGHTS

Ultralow noise and intermodulation distortion (IMD) enable

high quality waveform synthesis at intermediate frequencies up

to 200 MHz.

LVDS receivers support SDR or DDR modes, with the maxi-

mum conversion rate exceeding 600 MSPS.

Manufactured on a CMOS process, the AD9725 uses a proprie-

tary switching technique that enhances dynamic performance.

The current output of the AD9725 can be easily configured for

various single-ended or differential circuit topologies.