TTP252 datasheet(21/40 Pages) TONTEK

21 / 40 page

Preliminary

TTP252

TonTouch

12’/08/21

Page 21 of 40

Ver: 3.0

TBC (ADDRESS : 20DH) : Time base control register[R/W]

Bit3

Bit2

Bit1

Bit0

Default Value

Bit Name

TB2S

TB1S2

TB1S1

TB1S0

Read/Write

R/W

1111B

TB1S2 ~ TB1S0: Base timer1 overflow frequency selection bits.

TB2S: Base timer2 overflow frequency selection (0: 32Hz; 1:16Hz)

(Every time writing the TBRB will clear the time base counter)

TB2S

Base timer overflow

frequency (TB1OV)

TB2OV

(OSCL=16K)

TBCK/512

32Hz

TBCK/1024

16Hz

TB1S2 TB1S1 TB1S0

Base timer overflow

frequency (TB1OV)

TB1OV

(OSCL=16K)

TBCK

16KHZ

TBCK/2

8KHZ

TBCK/16

1KHZ

TBCK/64

256HZ

TBCK/256

64 HZ

TBCK/2048

8HZ

TBCK/8192

2HZ

TBCK/16384

1HZ

P-3: 8 bits Timer/Counter/PFD (TCP) for TCP1 &

8 bits

Timer/PWM/PFD (TCP) for TCP2

.Timer

When TCPx works as a Timer, user needs give the preload data TCPxD for

periodic interrupt. After initial setting, user starts the TCPx counting by setting

TCPxEN=1, the TCPx cycle period is:

Tc = (selected clock cycle) * (TCPxD)

When user writes data to the TCPxD, the data just keep in TCPxL/H register.

During the TCPxEN=1 command executed, the TCPxD’s complement value will

load into counter TCPx as initial value and start the timer function. Necessary

TCP1LD=1(just in TCP1), timer run with reload feature as TCPx up counts and

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