BCM4354 datasheet(184/192 Pages) CYPRESS

Part #	BCM4354

Description	Single-Chip 5G Wi-Fi IEEE 802.11ac 2횞2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver

PDF	192 Pages

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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184 / 192 page

Sequencing of Reset and Regulator Control Signals

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 183

Figure 50 shows the WLAN boot-up sequence from power-up to firmware download.

Figure 50: WLAN Boot-Up Sequence

< 950 µs

After 8 ms the reference clock is

assumed to be up. Access to PLL

registers is possible.

8 ms

< 4 ms

< 104 ms

After a fixed delay following Internal POR and WL_REG_ON going high,

the device responds to host F0 (address 0x14) reads.

VDDIO

WL_REG_ON

VDDC

(from internal PMU)

Internal POR

Device requests for reference clock

Host Interaction:

Host polls F0 (address 0x14) until it reads a

predefined pattern.

Host sets wake-up-wlan bit and

waits 8 ms, the maximum time for

reference clock availability.

After 8 ms, host programs PLL

registers to set crystal frequency

Host downloads

code.

Chip active interrupt is asserted after the PLL locks

VBAT*

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .

BCM4354 Datasheet(PDF) 184 Page - Cypress Semiconductor