PCI9060SD datasheet(87/192 Pages) ETC

87 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 78

Version 1.02

4.6 DMA REGISTERS

4.6.1 (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register

Table 4-62. (DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register

Field

Description

Read

Write

Value after Reset

1:0

Local Bus Width. Value of 00 indicates bus width of 8 bits, a value of 01 indicates

bus width of 16 bits and a value of 10 or 11 indicates bus width of 32 bits.

Yes

S = 01

J = 11

C = 11

5:2

Internal Wait States (data to data).

Yes

Ready Input Enable. Value of 1 enables Ready input. Value of 0 disables Ready

input.

Yes

BTERM# Input Enable. Value of 1 enables BTERM# input. Value of 0 disables

BTERM# input. If this bit is set to 0, PCI 9080 bursts four Lword maximum at a time.

Yes

Local Burst Enable. Value of 1 enables bursting. Value of 0 disables local bursting.

If burst is disabled, the local bus performs continuous single cycles for burst PCI

read/write cycles.

Yes

Chaining. Value of 1 indicates chaining mode is enabled. For chaining mode, the

DMA source address, destination address and byte count are loaded from memory

in PCI or Local Address Spaces. Value of 0 indicates nonchaining mode is enabled.

Yes

Done Interrupt Enable. Value of 1 enables interrupt when done. Value of 0 disables

interrupt when done. If DMA Clear Count mode is enabled, the interrupt won’t occur

until the byte count is cleared.

Yes

Local Addressing Mode. Value of 1 indicates local address LA[31:2] to be held

constant. Value of 0 indicates local address is incremented.

Yes

Demand Mode. Value of 1 causes DMA controller to operate in Demand mode. In

Demand mode, the DMA controller transfers data when its DREQ[1:0]# input is

asserted. It asserts DACK[1:0]# to indicate the current local bus transfer is in

response to the DREQ[1:0]# input. DMA controller transfers Lwords (32 bits) of

data. This may result in multiple transfers for an 8- or 16-bit bus.

Yes

Write and Invalidate Mode for DMA Transfers. When set to 1, PCI 9080 performs

Write and Invalidate cycles to the PCI bus. PCI 9080 supports Write and Invalidate

sizes of 8 or 16 Lwords. The size is specified in the PCI Cache Line Size Register.

If a size other than 8 or 16 is specified, PCI 9080 performs write transfers rather

than Write and Invalidate transfers. Transfers must start and end at the Cache Line

Boundaries.

Yes

DMA EOT (End of Transfer) Enable. Value of 1 enables EOT[1:0]# input pin. Value

of 0 disables EOT[1:0]# input pin. (Refer to Section 3.7.6.1, “End of Transfer

(EOT0# or EOT1#) Input.”)

Yes

DMA Stop Data Transfer Mode. Value of 0 sends a BLAST to terminate DMA

transfer. Value of 1 indicates an EOT asserted or DREQ[1:0]# negated during

demand mode DMA terminates the DMA transfer. (Refer to Section 3.7.6.1, “End of

Transfer (EOT0# or EOT1#) Input.”)

Yes

DMA Clear Count Mode. When set to 1, the byte count in each chaining descriptor,

if it is in local memory, is cleared when the corresponding DMA transfer is

complete.

Note:

If chaining descriptor is in PCI memory, the count is not cleared.

Yes

DMA Channel 0 Interrupt Select. Value of 1 routes the DMA Channel 0 interrupt to

the PCI interrupt. Value of 0 routes the DMA Channel 0 interrupt to the local bus

interrupt.

Yes

31:18

Reserved.

Yes

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