USBN9604SLB datasheet(39/60 Pages) NSC

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7.0 Register Set (Continued)

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A DMA request from a transmit endpoint is activated until the request condition clears. If DMOD is set to 0, DMA requests

are issued either until the firmware reads the respective Transmit Status (TXSx) register, thus resetting the TX_DONE bit,

or if the TX_LAST bit in the Transmit Command (TXCx) register is set by firmware. If DMOD is set to 1, DMA requests are

issued until the FIFO warning condition clears, either due to sufficient bytes being transferred to the endpoint, or if the

TX_DONE bit is set due to a transmission.

DMA requests from a receive endpoint are activated until the request condition clears. If DMOD is set to 0, DMA requests

are issued either until the firmware reads the respective Receive Status (RXSx) register, thus resetting the RX_LAST bit, or

if the endpoint FIFO becomes empty due to sufficient reads. If DMOD is set to 1, DMA requests are issued until the FIFO

warning condition clears, or if the endpoint FIFO becomes empty due to sufficient reads.

If DMOD is set to 0 and the endpoint and DMA are enabled, DMA requests are issued until the firmware reads the respective

TXSx or RXSx register, thus resetting the TX_DONE/RX_LAST bit. If DMOD is set to 1 and the endpoint and DMA are en-

abled, DMA requests are issued until the FIFO warning condition clears.

ADMA

Automatic DMA. Setting this bit automatically enables the selected receive or transmit endpoint. Before ADMA mode can be

enabled, the DEN bit in the DMA Control (DMACNTRL) register must be cleared. ADMA mode functions until any bit in the

DMA Event (DMAEV) register is set, except for NTGL. To initiate ADMA mode, all bits in the DMAEV register must be

cleared, except for NTGL.

For receive operations, the receiver is automatically enabled; when the packet is received, it is transferred via DMA to mem-

ory.

For transmit operations, the packet data is transferred via DMA from memory; then the transmitter is automatically enabled.

For ADMA operations, the DMOD bit is ignored. All operations proceed as if DMOD is set to 0.

When the device enters ADMA mode, any existing endpoint state may be lost. If there is already data in the FIFO, it is

flushed. The existing state of the RX_EN or TX_EN state may also change.

Clearing ADMA exits ADMA mode. DEN may either be cleared at the same time or later. If at the same time, all DMA oper-

ations cease immediately and firmware must transfer any remaining data. If later, the device completes any current DMA

operation before exiting ADMA mode (see the description of the DSHLT bit in the DMAEV register for more information).

DTGL

DMA Toggle. This bit is used to determine the initial state of ADMA operations. Firmware initially sets this bit to 1 if starting

with a DATA1 operation, and to a 0 if starting with a DATA0 operation.

Writes to this bit also update the NTGL bit in the DMAEV register.

IGNRXTGL

Ignore RX Toggle. If this bit is set, the compare between the NTGL bit in the DMAEV register and the TOGGLE bit in the

respective RXSx register is ignored during receive operations. In this case, a mismatch of both bits during a receive opera-

tion does not stop ADMA operation. If this bit is not set, the ADMA stops in case of a mismatch of the two toggle bits. After

reset, this bit is set to 0.

DEN

DMA Enable. This bit enables DMA mode when set. If this bit is reset and the current DMA cycle is completed (or was not

yet issued) the DMA transfer is terminated. When the device operates in serial interface mode (MODE1 pin is tied high) DMA

mode cannot be enabled, thus setting this bit has no effect. This bit is cleared on reset.

7.2.7

DMA Event Register (DMAEV)

The bits in this register are used with ADMA mode. Bits 0 to 3 may cause an interrupt if not cleared, even if the device is not

set to ADMA mode. Until all of these bits are cleared, ADMA mode cannot be initiated. Conversely, ADMA mode is automat-

ically terminated when any of these bits are set..

DSHLT

DMA Software Halt. This bit is set when ADMA operations have been halted by firmware. This bit is set only after the DMA

engine completes any necessary cleanup operations and returns to Idle state. The following conditions apply:

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Reserved

NTGL

Reserved

DSIZ

DCNT

DERR

DSHLT

-0

CoW

USBN9604SLB Datasheet(PDF) 39 Page - National Semiconductor (TI)

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