Electronic Components Datasheet Search
  English  ▼

X  

USBN9604SLB Datasheet(PDF) 13 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # USBN9604SLB
Description  Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

USBN9604SLB Datasheet(HTML) 13 Page - National Semiconductor (TI)

Back Button USBN9604SLB Datasheet HTML 9Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 10Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 11Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 12Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 13Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 14Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 15Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 16Page - National Semiconductor (TI) USBN9604SLB Datasheet HTML 17Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 60 page
background image
13
www.national.com
3.0
Parallel Interface
The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its ad-
dressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1.
3.1
NON-MULTIPLEXED MODE
Non-multiplexed mode uses the control pins CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown
in Figure 4. This mode is selected by tying both the MODE1 and MODE0 pins to GND.
The CPU has direct access to the DATA_IN, DATA_OUT and ADDR registers. Reading and writing data to the device can
be done either in standard access or burst mode. See Figure 5 for timing information.
Figure 5. Non-Multiplexed Mode Timing Diagram
CS
A0
WR
0x00
0x3F
DATA_IN
D7-0
RD
Data Out
Data In
Register File
DATA_OUT
ADDR
Address
Figure 4. Non-Multiplexed Mode Block Diagram
A0
CS
D7-0
Out
Input
RD
WR
Out
Write Address
Read Data
Burst Read Data



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com