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USBN9604SLB Datasheet(PDF) 13 Page - National Semiconductor (TI) |
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USBN9604SLB Datasheet(HTML) 13 Page - National Semiconductor (TI) |
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13 / 60 page ![]() 13 www.national.com 3.0 Parallel Interface The parallel interface allows the device to function as a CPU or microcontroller peripheral. This interface type and its ad- dressing mode (multiplexed or non-multiplexed) is determined via device input pins MODE0 and MODE1. 3.1 NON-MULTIPLEXED MODE Non-multiplexed mode uses the control pins CS, RD, WR, the address pin A0 and the bidirectional data bus D7-0 as shown in Figure 4. This mode is selected by tying both the MODE1 and MODE0 pins to GND. The CPU has direct access to the DATA_IN, DATA_OUT and ADDR registers. Reading and writing data to the device can be done either in standard access or burst mode. See Figure 5 for timing information. Figure 5. Non-Multiplexed Mode Timing Diagram CS A0 WR 0x00 0x3F DATA_IN D7-0 RD Data Out Data In Register File DATA_OUT ADDR Address Figure 4. Non-Multiplexed Mode Block Diagram A0 CS D7-0 Out Input RD WR Out Write Address Read Data Burst Read Data |
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