USBN9604SLB datasheet(4/60 Pages) NSC

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Table of Contents (Continued)

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7.1.2

Clock Configuration Register (CCONF)...................................................................... 31

7.1.3

Revision Identifier (RID) .............................................................................................. 31

7.1.4

Node Functional State Register (NFSR) ..................................................................... 32

7.1.5

Main Event Register (MAEV) ....................................................................................... 32

7.1.6

Main Mask Register (MAMSK) .................................................................................... 33

7.1.7

Alternate Event Register (ALTEV).............................................................................. 33

7.1.8

Alternate Mask Register (ALTMSK) ............................................................................ 34

7.1.9

Transmit Event Register (TXEV) ................................................................................. 34

7.1.10

Transmit Mask Register (TXMSK) ............................................................................... 35

7.1.11

Receive Event Register (RXEV) ................................................................................. 35

7.1.12

Receive Mask Register (RXMSK) ............................................................................... 35

7.1.13

NAK Event Register (NAKEV) .................................................................................... 36

7.1.14

NAK Mask Register (NAKMSK) ................................................................................... 36

7.2

TRANSFER REGISTERS .......................................................................................................... 36

7.2.1

FIFO Warning Event Register (FWEV) ....................................................................... 36

7.2.2

FIFO Warning Mask Register (FWMSK) ..................................................................... 37

7.2.3

Frame Number High Byte Register (FNH) .................................................................. 37

7.2.4

Frame Number Low Byte Register (FNL) .................................................................... 37

7.2.5

Function Address Register (FAR) ................................................................................ 38

7.2.6

DMA Control Register (DMACNTRL) .......................................................................... 38

7.2.7

DMA Event Register (DMAEV) .................................................................................... 39

7.2.8

DMA Mask Register (DMAMSK) ................................................................................. 40

7.2.9

Mirror Register (MIR) ................................................................................................... 41

7.2.10

DMA Count Register (DMACNT) ................................................................................. 41

7.2.11

DMA Error Register (DMAERR) .................................................................................. 41

7.2.12

Wake-Up Register (WKUP) ........................................................................................ 42

7.2.13

Endpoint Control 0 Register (EPC0) ............................................................................ 43

7.2.14

Transmit Status 0 Register (TXS0) ............................................................................. 43

7.2.15

Transmit Command 0 Register (TXC0) ..................................................................... 44

7.2.16

Transmit Data 0 Register (TXD0) ................................................................................ 44

7.2.17

Receive Status 0 Register (RXS0) .............................................................................. 44

7.2.18

Receive Command 0 Register (RXC0) ....................................................................... 45

7.2.19

Receive Data 0 Register (RXD0) ................................................................................ 45

7.2.20

Endpoint Control X Register (EPC1 to EPC6) ............................................................. 46

7.2.21

Transmit Status X Register (TXS1, TXS2, TXS3) ....................................................... 46

7.2.22

Transmit Command X Register (TXC1, TXC2, TXC3) ................................................ 47

7.2.23

Transmit Data X Register (TXD1, TXD2, TXD3) ......................................................... 48

7.2.24

Receive Status X Register (RXS1, RXS2, RXS3) ....................................................... 48

7.2.25

Receive Command X Register (RXC1, RXC2, RXC3) ................................................ 49

7.2.26

Receive Data X Register (RXD1, RXD2, RXD3) ......................................................... 50

USBN9604SLB Datasheet(PDF) 4 Page - National Semiconductor (TI)

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