ADS808 datasheet(13/24 Pages) TI1

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ADS808

SBAS179C

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CLK

ADS808

0.1

µF

1:1

Square Wave

Clock Source

FIGURE 11. Connecting a Ground Referenced Square Wave

Clock Source to the ADS808 Using a RF Trans-

former.

DIGITAL INPUTS AND OUTPUTS

CLOCK INPUT

Unlike most A/D converters, the ADS808 contains an internal

clock conditioning circuitry. This enables the converter to

adapt to a variety of application requirements and different

clock sources. Some interface examples are given in the

following section. With no input signal connected to either

clock pin, the threshold level is set to about +1.6V by the

on-chip resistive voltage divider, as shown in Figure 9. The

parallel combination of R1 || R2 and R3 || R4 sets the input

impedance of the clock inputs (CLK, CLK) to approximately

2.7k

Ω single-ended, or 5.4kΩ differentially. The associated

ground-referenced input capacitance is approximately 5pF

for each input. If a logic voltage other than the nominal +1.6V

is desired, the clock inputs can be externally driven to

establish an alternate threshold voltage.

8.5k

Ω

ADS808

8.5k

Ω

+5V

Ω

CLK

Ω

Applying a single-ended clock signal will provide satisfactory

results in many applications. However, unbalanced high-

speed logic signals often introduce a high amount of distur-

bances, such as ringing or ground bouncing. Also, a high

amplitude may cause the clock signal to have unsymmetrical

rise and fall times, potentially effecting the converter’s distor-

tion performance. Proper termination practice and a clean

PCB layout will help to keep those effects to a minimum.

To take full advantage of the excellent distortion performance

of the ADS808, it is recommended to drive the clock inputs

differentially. A low-level, differential clock improves the digi-

tal feedthrough immunity and minimizes the effect of modu-

lation between the signal and the clock. Figure 11 illustrates

a simple method of converting a square wave clock from

single-ended to differential using a RF transformer. Small

surface-mount transformers are readily available from sev-

eral manufacturers (e.g.: model ADT1-1 by Mini-Circuits). A

capacitor in series with the primary side may be inserted to

block any DC voltage present in the signal. Since the clock

inputs are self-biased, the secondary side connects directly

to the two clock inputs of the converter.

CLK

ADS808

47nF

TTL/CMOS

Clock Source

(3V/5V)

FIGURE 9. The Differential Clock Inputs are Internally Biased.

FIGURE 10. Single-Ended TTL/CMOS Clock Source.

The ADS808 can be interfaced to standard TTL or CMOS

logic and accepts 3V or 5V compliant logic levels. In this case,

the clock signal should be applied to the CLK input, while the

complementary clock input (CLK) should be bypassed to

ground by a low-inductance ceramic chip capacitor, as shown

in Figure 10. Depending on the quality of the signal, inserting

a series damping resistor may be beneficial to reduce ringing.

When digitizing at high sampling rates (fS > 50MHz), the clock

should have a 50% duty cycle (tH = tL) to maintain a good

distortion performance.

The clock inputs of the ADS808 can be connected in a

number of ways. However, the best performance is obtained

when the clock input pins are driven differentially. When

operating in this mode, the clock inputs accommodate signal

swings ranging from 2.5Vp-p down to 0.5Vp-p, differentially.

This allows direct interfacing of clock sources, such as

voltage-controlled crystal oscillators (VCXO) to the ADS808.

The advantage here is the elimination of external logic

usually necessary to convert the clock signal into a suitable

logic (TTL or CMOS) signal, that otherwise would create an

additional source of jitter. In any case, a very low-jitter clock

is fundamental to preserving the excellent AC performance

of the ADS808. The converter itself is specified for a very low

0.25ps (rms) jitter, characterizing the outstanding capability

of the internal clock and track-and-hold circuitry. Generally,

as the input frequency increases, the clock jitter becomes

more dominant in maintaining a good SNR. This is particu-

larly critical in IF sampling applications where the sampling

frequency is lower than the input frequency (or

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