CC113LRGPR datasheet(15/86 Pages) TI1

15 / 86 page

LNA

BIAS

RBIAS

XOSC_Q1 XOSC_Q2

CSn

SO (GDO1)

XOSC

SCLK

FREQ

SYNTH

Radio Control

GDO0

ADC

RF_P

RF_N

GDO2

CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

Detailed Description

5.1

Overview

CC113L features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA)

and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are

digitized by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation, and bit/packet

synchronization are performed digitally.

The frequency synthesizer includes a completely on-chip LC VCO and a 90-degree phase shifter for

generating the I and Q LO signals to the down-conversion mixers in receive mode.

A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference

frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A 4-wire SPI is used for configuration and data buffer access.

The digital baseband includes support for channel configuration, packet handling, and data buffering.

5.2

Functional Block Diagram

A simplified block diagram of CC113L is shown in Figure 5-1.

Figure 5-1. CC113L Simplified Block Diagram

Detailed Description

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CC113LRGPR Datasheet(PDF) 15 Page - Texas Instruments