CC1100-RTR1 datasheet(35/100 Pages) TI1

35 / 100 page

CC1100

SWRS038D

Page 35 of 92

transmitted,

the

radio

will

enter

TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed

will not restart TX mode.

If whitening is enabled, everything following

the sync words will be whitened. This is done

before the optional FEC/Interleaver stage.

Whitening

enabled

setting

PKTCTRL0.WHITE_DATA=1

If FEC/Interleaving is enabled, everything

following the sync words will be scrambled by

the interleaver and FEC encoded before being

modulated. FEC is enabled by setting

MDMCFG1.FEC_EN=1

15.5 Packet Handling in Receive Mode

In receive mode, the demodulator and packet

handler will search for a valid preamble and

the sync word. When found, the demodulator

has obtained both bit and byte synchronism

and will receive the first payload byte.

If FEC/Interleaving is enabled, the FEC

decoder will start to decode the first payload

byte. The interleaver will de-scramble the bits

before any other processing is done to the

data.

If whitening is enabled, the data will be de-

whitened at this stage.

When variable packet length mode is enabled,

the first byte is the length byte. The packet

handler stores this value as the packet length

and receives the number of bytes indicated by

the length byte. If fixed packet length mode is

used, the packet handler will accept the

programmed number of bytes.

Next, the packet handler optionally checks the

address and only continues the reception if the

address matches. If automatic CRC check is

enabled, the packet handler computes CRC

and matches it with the appended CRC

checksum.

At the end of the payload, the packet handler

will optionally write two extra packet status

bytes (see Table 21 and Table 22) that contain

CRC status, link quality indication, and RSSI

value.

15.6 Packet Handling in Firmware

When implementing a packet oriented radio

protocol in firmware, the MCU needs to know

when a packet has been received/transmitted.

Additionally, for packets longer than 64 bytes

the RX FIFO needs to be read while in RX and

the TX FIFO needs to be refilled while in TX.

This means that the MCU needs to know the

number of bytes that can be read from or

written to the RX FIFO and TX FIFO

respectively. There are two possible solutions

to get the necessary status information:

a) Interrupt Driven Solution

In both RX and TX one can use one of the

GDO pins to give an interrupt when a sync

word has been received/transmitted and/or

when

complete

packet

has

been

received/transmitted

(IOCFGx.GDOx_CFG=0x06). In addition, there

are

configurations

for

the

IOCFGx.GDOx_CFG

that

are

associated

with

the

FIFO

(IOCFGx.GDOx_CFG=0x00

and

IOCFGx.GDOx_CFG=0x01

) and two that are

associated

with

the

FIFO

(IOCFGx.GDOx_CFG=0x02

and

IOCFGx.GDOx_CFG=0x03

) that can be used

as interrupt sources to provide information on

how many bytes are in the RX FIFO and TX

FIFO respectively. See Table 34.

b) SPI Polling

The PKTSTATUS register can be polled at a

given rate to get information about the current

GDO2 and GDO0 values respectively. The

RXBYTES

and TXBYTES registers can be

polled at a given rate to get information about

the number of bytes in the RX FIFO and TX

FIFO respectively. Alternatively, the number of

bytes in the RX FIFO and TX FIFO can be

read from the chip status byte returned on the

MISO line each time a header byte, data byte,

or command strobe is sent on the SPI bus.

It is recommended to employ an interrupt

driven solution as high rate SPI polling will

reduce the RX sensitivity. Furthermore, as

explained in Section 10.3 and the

CC1100

Errata Notes [1], when using SPI polling there

is a small, but finite, probability that a single

read from registers PKTSTATUS , RXBYTES

and TXBYTES is being corrupt. The same is

the case when reading the chip status byte.

Refer to the TI website for SW examples ([8]

and [9]).

CC1100-RTR1 Datasheet(PDF) 35 Page - Texas Instruments

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