CC1100-RTR1 datasheet(54/100 Pages) TI1

54 / 100 page

CC1100

SWRS038D

Page 54 of 92

27.1 Reference Signal

The chip can alternatively be operated with a

reference signal from 26 to 27 MHz instead of

a crystal. This input clock can either be a full-

swing digital signal (0 V to VDD) or a sine

wave of maximum 1 V peak-peak amplitude.

The reference signal must be connected to the

XOSC_Q1 input. The sine wave must be

connected to XOSC_Q1 using a serial

capacitor. When using a full-swing digital

signal this capacitor can be omitted. The

XOSC_Q2 line must be left un-connected. C81

and C101 can be omitted when using a

reference signal.

External RF Match

The balanced RF input and output of

CC1100

share two common pins and are designed for

a simple, low-cost matching and balun network

on the printed circuit board. The receive- and

transmit switching at the

CC1100 front-end is

controlled by a dedicated on-chip function,

eliminating the need for an external RX/TX-

switch.

A few passive external components combined

with the internal RX/TX switch/termination

circuitry ensures match in both RX and TX

mode.

Although

CC1100 has a balanced RF

input/output, the chip can be connected to a

single-ended antenna with few external low

cost capacitors and inductors.

The

passive

matching/filtering

network

connected to

CC1100 should have the following

differential impedance as seen from the RF-

port (RF_P and RF_N) towards the antenna:

Zout 315 MHz = 122 + j31 Ω

Zout 433 MHz = 116 + j41 Ω

Zout 868/915 MHz = 86.5 + j43 Ω

To ensure optimal matching of the

CC1100

differential output it is recommended to follow

the CC1100EM reference design ([5] or [6]) as

closely as possible. Gerber files for the

reference designs are available for download

from the TI website.

PCB Layout Recommendations

The top layer should be used for signal

routing, and the open areas should be filled

with metallization connected to ground using

several vias.

The area under the chip is used for grounding

and shall be connected to the bottom ground

plane with several vias. In the CC1100EM

reference designs ([5] and [6]) we have placed

5 vias inside the exposed die attached pad.

These vias should be “tented” (covered with

solder mask) on the component side of the

PCB to avoid migration of solder through the

vias during the solder reflow process.

The solder paste coverage should not be

100%. If it is, out gassing may occur during the

reflow process, which may cause defects

(splattering, solder balling). Using “tented” vias

reduces the solder paste coverage below

100%.

See Figure 29 for top solder resist and top

paste masks.

Each decoupling capacitor should be placed

as close as possible to the supply pin it is

supposed to decouple. Each decoupling

capacitor should be connected to the power

line (or power plane) by separate vias. The

best routing is from the power line (or power

plane) to the decoupling capacitor and then to

the

CC1100 supply pin. Supply power filtering is

very important.

Each decoupling capacitor ground pad should

be connected to the ground plane using a

separate via.

Direct connections between

neighboring power pins will increase noise

coupling and should be avoided unless

absolutely necessary.

The external components should ideally be as

small as possible (0402 is recommended) and

surface

mount

devices

are

highly

recommended. Please note that components

smaller than those specified may have

differing characteristics.

Precaution should be used when placing the

microcontroller in order to avoid noise

interfering with the RF circuitry.

A CC1100/1150DK Development Kit with a

fully

assembled

CC1100EM

Evaluation

Module is available. It is strongly advised that

this reference layout is followed very closely in

order to get the best performance. The

schematic, BOM and layout Gerber files are all

available from the TI website ([5] and [6]).

CC1100-RTR1 Datasheet(PDF) 54 Page - Texas Instruments

CC1100-RTR1 Datasheet(HTML) 54 Page - Texas Instruments

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