AM1802 datasheet(14/182 Pages) TI1

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EMA_D[15]/

GP3[7]

AXR15/

GP0[7]

ACLKR/

GP0[15]

ACLKX/

GP0[14]

AHCLKX/

USB_REFCLKIN/

GP0[10]

UART1_CTS

AFSX/

GP0[12]

AFSR/

GP0[13]

AXR9/

GP0[1]

AXR4/

GP1[12]/

MII_COL

AXR5/

GP1[13]/

MII_TXCLK

AXR7/

GP1[15]

AXR10/

GP0[2]

AXR1/

GP1[9]/

MII_TXD[1]

AXR3/

GP1[11]/

MII_TXD[3]

AXR2/

GP1[10]/

MII_TXD[2]

GP8[10]

RTC_ALARM/

GP0[8]/

UART2_CTS

DEEPSLEEP

AXR0/

GP8[7]/

MII_TXD[0]

GP8[14]

GP8[8]

VSS

GP8[12]

AXR8/

GP0[0]

AXR12/

GP0[4]

EMA_D[4]/

GP4[12]

AXR14/

GP0[6]

EMA_WEN_DQM[1]/

GP2[2]

EMA_D[0]/

GP4[8]

EMA_A[19]/

MMCSD0_DAT[2]/

GP4[3]

EMA_D[9]/

GP3[1]

EMA_A_R

GP3[9]

MMCSD0_CLK/

GP4[7]

EMA_D[8]/

GP3[0]

EMA_D[13]/

GP3[5]

GP6[4]

GP6[2]

AMUTE/

GP0[9]

UART2_RTS/

DVDD3318_A

EMA_WE/

GP3[11]

EMA_D[10]/

GP3[2]

EMA_D[3]/

GP4[11]

EMA_SDCKE/

GP2[6]

EMA_D[14]/

GP3[6]

EMA_D[7]/

GP4[15]

EMA_D[1]/

GP4[9]

EMA_A[22]/

MMCSD0_CMD/

GP4[6]

EMA_D[2]/

GP4[10]

EMA_A[21]/

MMCSD0_DAT[0]/

GP4[5]

GP8[13]

AHCLKR/

GP0[11]

UART1_RTS

EMA_D[12]/

GP3[4]

EMA_WEN_DQM[0]/

GP2[3]

EMA_CLK/

GP2[7]

AXR6/

GP1[14]/

MII_TXEN

AXR11/

GP0[3]

EMA_D[6]/

GP4[14]

EMA_D[11]/

GP3[3]

RVDD

EMA_D[5]/

GP4[13]

GP8[11]

GP8[9]

GP8[15]

AXR13/

GP0[5]

EMA_CS[4]/

GP3[13]

EMA_CAS/

GP2[4]

DVDD3318_B

DVDD18

CVDD

DVDD3318_B

DVDD18

VSS

DVDD3318_A

VSS

CVDD

VSS

CVDD

NC_J1

NC_J2

DVDD3318_C

CVDD

VSS

AM1802

SPRS710E – NOVEMBER 2010 – REVISED MARCH 2014

www.ti.com

Figure 3-4. Pin Map (Quad D)

3.6

Pin Multiplexing Control

Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.

For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed

with several different functions has a corresponding 4-bit field in one of the PINMUX registers.

Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data

and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'

of the peripheral functions in which case the pin's IO buffer is held tri-stated.

Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX

registers have no effect on input from a pin.

Device Overview

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