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DM385 Datasheet(PDF) 156 Page - Texas Instruments

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Part # DM385
Description  DaVinci Digital Media Processor
PDF  281 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DM385 Datasheet(HTML) 156 Page - Texas Instruments

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DM385, DM388
SPRS821D – MARCH 2013 – REVISED DECEMBER 2013
www.ti.com
Table 7-23. PLL CLKOUT Frequency Ranges (continued)
OPP100
PLL
UNIT
MIN
MAX
PLL_DDR
10
400
MHz
PLL_HDVPSS
10
200
MHz
PLL_AUDIO
10
200
MHz
PLL_MEDIACTL
10
400
MHz
PLL_USB
10(1)
960
MHz
PLL_VIDEO0
10
200
MHz
PLL_VIDEO1
10
200
MHz
PLL_VIDEO2
10
200
MHz
(1)
When the USB is used, PLL_USB must be fixed at 960 MHz.
7.4.6.4
PLL Register Description(s)
The PLL Control Registers reside in the Control Module and are listed in Section 4.1, Control Module of
this datasheet.
7.4.7
SYSCLKs
In some cases, the system clock inputs and PLL outputs are sent to the PRCM Module for division and
multiplexing before being routed to the various device Modules. These clock outputs from the PRCM
Module are called SYSCLKs. Table Table 7-24 lists the device SYSCLKs along with their maximum
supported clock frequencies. In addition, limits shown in these tables may be further restricted by the clock
frequency limitations of the device modules using these clocks. For more details on Module Clock
frequency limits, see Section 7.4.8 Module Clocks.
NOTE
For supported OPP frequencies, see Table 7-3, Device Operating Points (OPPs).
Table 7-24. Maximum SYSCLK Clock Frequencies
MAX CLOCK FREQUENCY
SYSCLK
OPP100 (MHz)
SYSCLK1
RSV
SYSCLK2
RSV
SYSCLK3
266
SYSCLK4
220
SYSCLK5
RSV
SYSCLK6
110
SYSCLK7
RSV
SYSCLK8
192
SYSCLK9
RSV
SYSCLK10
48
SYSCLK11
RSV
SYSCLK12
RSV
SYSCLK13
RSV
SYSCLK14
27
SYSCLK15
RSV
SYSCLK16
27
SYSCLK17
RSV
156
Power, Reset, Clocking, and Interrupts
Copyright © 2013, Texas Instruments Incorporated
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