AD5641 datasheet(12/20 Pages) AD

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AD5641

Preliminary Technical Data

Rev. PrC | Page 12 of 20

GENERAL DESCRIPTION

D/A SECTION

The AD5641 DAC is fabricated on a CMOS process. The

architecture consists of a string DAC followed by an output

buffer amplifier. Figure 24 is a block diagram of the DAC

architecture.

VDD

VOUT

GND

RESISTOR

NETWORK

REF (+)

REF (–)

OUTPUT

AMPLIFIER

DAC REGISTER

Figure 24. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by

⎟

⎠

⎞

⎜

⎝

⎛

16384

OUT

where D is the decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 16,384.

RESISTOR STRING

The resistor string section is shown in Figure 25. It is simply a

string of resistors, each of value R. The code loaded to the DAC

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaran-

teed monotonic.

TO OUTPUT

AMPLIFIER

Figure 25. Resistor String Section

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output, giving an output range of 0 V to VDD. It is

capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

can be seen in Figure 10. The slew rate is 0.5 V/µs, with a half-

scale settling time of 8 µs with the output unloaded.

SERIAL INTERFACE

The AD5641 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 16-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5641compatible with high speed

DSPs. On the 16th falling clock edge, the last data bit is clocked

in and the programmed function is executed (a change in DAC

this stage, the SYNC line might be kept low or brought high. In

either case, it must be brought high for a minimum of 33 ns

before the next write sequence so that a falling edge of SYNC

can initiate the next write sequence.

Because the SYNC buffer draws more current when VIN = 1.8 V

than it does when VIN = 0.8 V, SYNC should be idled low

between write sequences for even lower power operation of the

part, as mentioned above. However, it must be brought high

again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 26). The first

two bits are control bits that determine the part’s mode of

operation (normal mode or any one of three power-down

modes). For a complete description of the various modes, see

the Power-Down Modes section. The next 16 bits are the data

bits, which are transferred to the DAC register on the 16th falling

edge of SCLK.

DATA BITS

DB15 (MSB)

DB0 (LSB)

PD1

PD0

D13

D12

D11

D10

NORMAL OPERATION

1 k

Ω TO GND

100 k

Ω TO GND

THREE-STATE

POWER-DOWN MODES

Figure 26. Input Register Contents

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