AD5660 datasheet(7/20 Pages) AD

Part #	AD5660

Description	3 V/5 V, 16-Bit nanoDACTM D/A with 10 ppm/째C Max On-Chip Reference in SOT-23

PDF	20 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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7 / 20 page

Preliminary Technical Data

AD5660

Rev. PrJ | Page 7 of 20

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Limit at TMIN, TMAX

Parameter

VDD = 2.7 V to 3.6 V

VDD = 3.6 V to 5.5 V

Unit

Conditions/Comments

t1 1

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

SYNC to SCLK Falling Edge Setup Time

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

SCLK Falling Edge to SYNC Rising Edge

ns min

Minimum SYNC High Time

ns min

SYNC Rising Edge to SCLK Fall Ignore

t10

ns min

SCLK Falling Edge to SYNC Fall Ignore

1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

Figure 2. Serial Write Operation

AD5660 Datasheet(PDF) 7 Page - Analog Devices