AD5660 datasheet(14/20 Pages) AD

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AD5660

Preliminary Technical Data

Rev. PrJ Page 14 of 20

THEORY OF OPERATION

D/A SECTION

The AD5660 DAC is fabricated on a CMOS process. The

architecture consists of a string DAC followed by an output

buffer amplifier. The parts include an internal 1.25 V/2.5 V,

10 ppm/°C reference with an internal gain of two. Figure 22

shows a block diagram of the DAC architecture.

Figure 22. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal

output voltage is given by:

⎟

⎠

⎞

⎜

⎝

⎛

65536

xVREF

OUT

where D = the decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 65535.

Figure 23. Resistor String

RESISTOR STRING

The resistor string section is shown in Figure 23. It is simply a

string of resistors, each of value R. The code loaded to the DAC

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output which gives an output range of 0 V to VDD.

It is capable of driving a load of 2 kΩ in parallel with 1000 pF to

GND. The source and sink capabilities of the output amplifier

can be seen in Figure 10 and Figure 11. The slew rate is 1 V/µs

with a half-scale settling time of 8 µs with the output unloaded.

SERIAL INTERFACE

The AD5660 has a 3-wire serial interface (SYNC, SCLK and

DIN), which is compatible with SPI, QSPI and MICROWIRE

interface standards as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5660compatible with high speed

DSPs. On the 24th falling clock edge, the last data bit is clocked

in and the programmed function is executed, that is, a change in

DAC register contents and/or a change in the mode of

operation. At this stage, the SYNC line may be kept low or be

brought high. In either case, it must be brought high for a

minimum of 33 ns before the next write sequence so that a

falling edge of SYNC can initiate the next write sequence. Since

the SYNC buffer draws more current when VIN = 2.4 V than it

does when VIN = 0.8 V, SYNC should be idled low between write

sequences for even lower power operation of the part. As is

mentioned above, however, it must be brought high again just

before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 24). The first

six bits are “don’t cares.” The next two are control bits that

control which mode of operation the part is in (normal mode

or any one of three power-down modes). There is a more

complete description of the various modes in the Power-Down

Modes section. The next sixteen bits are the data bits. These are

transferred to the DAC register on the24th falling edge of

SCLK.

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