AD9860 datasheet(14/32 Pages) AD

14 / 32 page

REV. 0

–14–

AD9860/AD9862

Setting this bit high enables the decimation filters and decimates

the receive data by two.

BIT 5: Alt Timing Mode

The timing section in the data sheet describes two timing modes,

the “Normal Operation” and the “Alternate Operation” modes.

At power up, the default configuration is established from the

logic level of the Mode/TxBlank pin. If Mode/TxBlank is logic

low, the Normal Operation mode is the default; if the Mode/

TxBlank pin is held at a logic high, the Alternative Operation

mode is configured at power-up (the DLL is forced to multiply

by 4 at power-up by default in this mode). After power up, the

operation mode can be configured so that the Mode/TxBlank pin

can be used for other functions. To allow this, set this bit high.

BIT 4: TxOff Enable

By default, the Mode/TxBlank pin is not used for any transmit

synchronization. The Mode/TxBlank pin input can be used to

serve two functions, blanking the DAC outputs and slaving the

TxPGA gain control. When this bit is set high, a logic high on the

Mode/TxBlank pin forces the Tx digital block to stop clocking. In

this mode, the Tx outputs will be static, holding their last update

values. To slave the TxPGA gain control to the Mode/TxBlank

pin input, register Slave Enable (Register 17, Bit 1) needs to also

be programmed. See that register for more information.

BIT 3: Tx Digital (Power-Down)

By default this bit is low, enabling the transmit path digital to

operate as programmed through other registers. By setting this

bit high, the digital blocks are not clocked to reduce power con-

sumption. When enabled, the Tx outputs will be static, holding

their last update values.

BIT 0-2: Tx Analog (Power-Down)

Three options are available to reduce analog power consumption

for the Tx channels. The first two options disable the analog output

from Tx channel A or B independently, and the third option

disables the output of both channels and reduces the power

consumption of some of the additional analog support circuitry

for maximum power savings. With all three options, the DAC bias

current is not powered down so recovery times are fast (typically

a few clock cycles). The list below explains the different modes

and settings used to configure them.

Tx Analog

Power-Down

Power-Down Option

Bits Setting [2:0]

Power-Down Tx B Channel Analog Output

[1 0 0]

Power-Down Tx A Channel Analog Output

[0 1 0]

Power-Down Tx A and Tx B Analog Outputs [1 1 1]

DAC A/DAC B Offset

These 10-bit, twos complement registers control a dc current

offset that is combined with the Tx A or Tx B output signal. An

offset current of up to

±12% IOUTFS (2.4 mA for a 20 mA full-

scale output) can be applied to either differential pin on each

channel. The offset current can be used to compensate for offsets

that are present in an external mixer stage, reducing LO leakage

at its output. Default setting is hex00, no offset current. The

offset current magnitude is set using the lower nine bits. Setting

the MSB high will add the offset current to the selected differen-

tial pin, while an MSB low setting will subtract the offset value.

DAC A/DAC B Offset Direction

This bit determines to which of the differential output pins for

the selected channel the offset current will be applied. Setting this

bit low will apply the offset to the negative differential pin. Setting

this bit high will apply the offset to the positive differential pin.

BIT 6, 7: DAC A/DAC B Coarse Gain Control

These register bits will scale the full-scale output current (IOUTFS)

of either Tx channel independently. IOUT of the Tx channels is a

function of the RSET resistor, the TxPGA setting, and the Coarse

Gain Control setting.

MSB, LSB

Tx Channel Current Scaling

10 or 11

Does not scale output current

Scales output current by 1/2

Scales output current by 1/11

BIT 5–0: DAC A/DAC B Fine Gain

The DAC output curve can be adjusted fractionally through the

Gain Trim Control. Gain trim of up to

±4% can be achieved on

each channel individually. The Gain Trim register bits are a twos

complement attention control word.

MSB, LSB

100000

Maximum positive gain adjustment

111111

Minimum positive gain adjustment

000000

No adjustment (default)

000001

Minimum negative gain adjustment

011111

Maximum negative gain adjustment

BIT 0–7: TxPGA Gain

This 8 bit, straight binary (Bit 0 is the LSB, Bit 7 is the MSB) reg-

ister controls for the Tx programmable gain amplifier (TxPGA).

The TxPGA provides a 20 dB continuous gain range with 0.1 dB

steps (linear in dB) simultaneously to both Tx channels. By

default, this register setting is hex00.

MSB, LSB

000000

Minimum gain scaling –20 dB

111111

Maximum gain scaling 0 dB

BIT 1: Slave Enable

The TxPGA Gain is controlled through register TxPGA Gain

setting and by default is updated immediately after the register

write. If this bit is set, the TxPGA Gain update is synchronized

with the rising edge of a signal applied to the Mode/TxBlank

pin. Setting TxOff enable in Register 8 is also required.

BIT 0: TxPGA Fast (Update Mode)

The TxPGA Fast bit controls the update speed of the TxPGA.

When Fast Update mode is enabled, the TxPGA provides fast gain

settling within a few clock cycles. Default setting for this bit

is low, which indicates Normal Update mode. Fast mode is

enabled when this bit is set high.

BIT 6: Tx Retime

The Tx path can use either of the clock outputs, CLKOUT1 or

CLKOUT2, to latch the Tx input data. Since CLKOUT1 and

CLKOUT2 have slight phase offsets, this provides some timing

flexibility with the interface. By default, this bit is high and the

Tx input latches use CLKOUT1. Setting this bit low will force

the Tx latches to use CLKOUT2.

AD9860 Datasheet(PDF) 14 Page - Analog Devices

AD9860 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL