AD9860 datasheet(24/32 Pages) AD

24 / 32 page

REV. 0

–24–

AD9860/AD9862

The output will be latched using some configuration of CLKOUT1

or CLKOUT2 edges as defined in the Clock Overview section of

the data sheet. The Rx path available options include bypassing

the input buffer, RxPGA control and using the decimation filter.

The input buffer description above explains the conditions under

which the buffer should be bypassed.

If the input signal, or the undersampled alias signal for the

IF sampling case, falls below 40% of the ADC Nyquist rate, the

decimation filter can be enabled to suppress out-of-band noise

and spurious signals by 40 dB or more. With the decimation

filter enabled the SNR of the Rx path improves by about 2.3 dB.

Dual Channel Complex ADC Signal

The Dual Channel Complex ADC Signal mode is used to receive

baseband I and Q signals or a single sideband signal at some IF.

In this mode, a complex input signal is generated from an external

quadrature demodulator. The in-phase channel (I channel) is

connected to VIN+A and VIN–A, and the Quadrature Data

(Q channel) is connected to the VIN+B and VIN–B differential

pins. The Rx path available options include bypassing the input

buffer, RxPGA control, the decimation filter, and using the digital

Hilbert filter. Shared Reference mode is also discussed below.

The RxPGA provides 0 dB to 20 dB gain control for both chan-

nels. The input buffer description above explains the conditions

under which the buffer should be bypassed.

If the input signal, or the undersampled alias signal for the IF sam-

pling case, falls below 40% of the ADC Nyquist rate, the decimation

filter can be enabled to suppress out-of-band noise and spurious

signals by 40 dB or more. With the decimation filter enabled,

the SNR of the Rx path improves by about 2.3 dB.

A digital Hilbert filter can be enabled to provide a receive image

rejection architecture on-chip. The digital Hilbert filter combines

the I data and a phase shifted version of the Q data to produce a

single combined Rx signal. The filter can provide 50 dB image

suppression in the pass band (less than 0.1 dB ripple). The pass

band of the filter is from 25% to 75% of Nyquist rate of the data

entering the Hilbert filter. Note, the Hilbert filter’s maximum

input data rate is 32 MSPS, at ADC rates above 32 MSPS. The

decimation filter is required to reduce the data rate. With the

decimation filter also enabled, the pass band of the Hilbert filter

will be 12.5% to 37.5% of the ADC Nyquist rate (still 25% to 75%

of the Nyquist rate of the data entering the Hilbert filter).

An optional Shared Reference mode allows the user to connect the

differential references from the dual ADC together externally for

superior gain matching performance. To enable the Shared Ref-

erence mode, the Shared Ref register (d4, b1) should be set high.

TIMING GENERATION BLOCK

The AD9860/AD9862 Timing Generation block uses a single

external clock reference to derive all internal clocks to operate

the transmit and receive channels. The input clock reference

can consist of either an external single ended clock applied to

the OSC1 pin, with the OSC2 pin left floating or an external

crystal connected between the clock input pins (OSC1 and OSC2).

By default, the AD9860/AD9862 can accept either an external

reference clock or a crystal to generate the input clock. The

internal oscillator, if not used, should be disabled by setting the

Input Control Clock register. The OSC1 input impedance is a

relatively high resistive impedance (typically, about 500 k

W).

An internal Delay Lock Loop (DLL) based clock multiplier pro-

vides a low noise, 2

or 4

multiplication of the input clock over

an output frequency range of 32 MHz to 128 MHz. The DLL

Fast register should be used to optimize the DLL performance.

For DLL output frequencies between 32 MHz and 64 MHz, this

bit should be set low. For output frequencies between 64 MHz

to 128 MHz, the Fast bit should be set high (for a 64 MHz out-

put frequency, the register can be set either high or low). The DLL

can be bypassed by setting a 1

multiplication factor in the DLL

Multiplier register. The DLL can be powered down when it is

bypassed for power savings by setting the DLL PwrDwn register.

For applications where an external crystal is desired, the AD9860/

AD9862 internal oscillator circuit and the DLL clock multiplier

enable a low frequency, lower cost quartz crystal to be used to

generate the input reference clock. The quartz crystal would be

connected between the OSC1 and OSC2 pins with parallel

resonant load capacitors as specified by the crystal manufacturer.

An internal Duty Cycle Stabilizer (DCS) can be enabled on the

AD9860 by setting the Clk Duty register. This provides a stable

50% duty cycle to the ADC for high speed clock rates between

40 MSPS to 64 MSPS when proper duty cycle is more critical.

System Clock Distribution Circuitry

There are many variables involved in the timing distribution.

External variables include CLKIN, CLKOUT1, CLKOUT2,

Rx Data Rate, Tx Data Rate. Internal variables include ADC

conversion rate, DAC update rate, interpolation rate, decimation

rate, Rx data multiplexing and Tx data demultiplexing. Many of

these parameters are interrelated and based on CLKIN. Optimal

power versus performance and ease of integration options can

be chosen to suit a particular application.

ADC

DATA

MUX

AND

LATCH

DATA

LATCH

AND

DEMUX

NO DECIMATION,

DECIMATE:

REG D6 B0

MUX OUT:

REG D5 B0

Rx RETIME:

REG D5 B3

2 DATA PATHS: REG D19 B4

Q/I ORDER:

REG D18 B5

Tx RETIME:

REG D18 B6

NO INTERP

2, 4

INTERPOLATION:

REG D19 B0, 1

DIV

INV

NO INVERSION,

INVERT

INV1: REG D25 B1

1 , 1/2

CLKSEL

1 , 1/2

ADC DIV2:

REG D24 B5

DLL MULTIPLIER:

REG D24 B3, 4

DIV

INV

DLL

DIV

1 , 1/2 , 1/4

NO INVERSION,

INVERT

INV2:

REG D25 B5

1 , 2 , 4

CLKOUT2

DIV FACTOR:

REG 25 B6, 7

DAC

CLOCK PATH

DATA PATH

CLKIN

Rx DATA

[0:23]

CLKOUT1

CLKOUT2

Tx DATA

[0:13]

Figure 8. Normal Operation Timing Block Diagram

One of two possible timing operation modes can be selected. The

typical timing mode is called Normal Operation mode; a block

diagram is shown in Figure 8. The other mode is called Alterna-

tive Operation mode, and a block diagram is shown in Figure 12.

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