AD9860 datasheet(27/32 Pages) AD

27 / 32 page

REV. 0

AD9860/AD9862

–27–

Tx Path (Normal Operation)

The DAC update rate, the Tx input data rate, and the rate of

CLKOUT2 (clock used to latch Tx input data) are the parameters

of interest for the transmit path data. These parameters, in addition

to the output signal bandwidth, are related to CLKIN by the settings

of the ADC Div2, the DLL multiplier, the CLKOUT2 Div, the

two edges, and the interpolation registers.

The Tx data is timed relative to the CLKOUT2 pin (unless it is

retimed relative to CLKOUT1 by setting Tx Retime register) and

the input Tx data is latched on either each rising edge, each

falling edge or both edges (controlled through the Inverse Sample

and two edges registers). The timing diagrams for these cases

are shown in Figure 12.

The Dual Tx data is multiplexed onto a single bus so that fewer

digital bits are necessary to transfer data. Throughout this discus-

sion of Tx path timing, Tx digital processing options other than

interpolation are ignored because they do not change data timing;

Tx data timing reflects whether single or dual channel data is

latched into the AD9860/AD9862.

The rates of CLKOUT2 (and the input data rate) are related

to CLKIN by the DLL Multiplier Register, the setting of the

CLKOUT2 Divide Factor Register and the register ADC Div2.

These relationships are shown in Table II.

Table II. CLKOUT2 Timing Relative to CLKIN

for Normal Operation Mode

DLL

CLKOUT2

CLK DIV2

Mult

Div Factor

CLKOUT2

CLKIN

2CLKIN/2

4CLKIN/4

12 CLKIN

No Div

CLKIN

4CLKIN/2

14 CLKIN

22 CLKIN

CLKIN

1CLKIN/2

2CLKIN/4

4CLKIN/8

CLKIN

Div by 2

2CLKIN/2

4CLKIN/4

12 CLKIN

CLKIN

4CLKIN/2

ADC

DATA MUX

AND

LATCH

DATA LATCH

AND

DEMUX

NO DECIMATION,

DECIMATE:

REG D6 B0

MUX OUT: REG D5 B0

Rx RETIME: REG D5 B3

2 DATA PATHS: REG D19 B4

Q/I ORDER: REG D18 B5

Tx RETIME: REG D18 B6

NO INTERP, 2, 4

INTERPOLATION:

REG D19 B0, 1

INV

NO INVERSION, INVERT

INV1: REG D25 B1

INV

DIV

1 , 1/2 , 1/4

NO INVERSION, INVERT

INV2: REG D25 B5

CLKOUT2 DIV FACTOR:

REG 25 B6, 7

DAC

CLKIN

Rx DATA

[0:23]

CLKOUT1

CLKOUT2

Tx DATA

[0:13]

DLL MULTIPLIER:

REG D24 B3, 4

DLL

1 , 2 , 4

DIV

1 , 1/2

CLKSEL

1 , 1/2

ADC DIV2:

REG D24 B5

DIV

CLOCK PATH

DATA PATH

Figure 13. Alternative Operation Timing Block Diagram

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