AD9860 datasheet(26/32 Pages) AD

26 / 32 page

REV. 0

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AD9860/AD9862

For the Normal Operation mode, the Tx timing is based on

a clock derived from the DLL output, while the Rx clock is

unaffected by the DLL setting.

The Alternative Operation mode, timing utilizes the output of

the DLL to generate both Rx and Tx clocks. It also sets default

operation of the DLL to 4

mode.

Normal Operation is typically recommended because the Rx ADC

is more sensitive to the jitter and noise that the DLL may gener-

ate, so its performance may degrade. The Mode/TxBlank pin

logic level at power up or RESET defines in which mode the

device powers up. If Mode/TxBlank is low at power up, the

Normal Operation mode is configured. Otherwise, the Alternative

Operation mode is configured.

Rx Path (Normal Operation)

The ADC sampling rate, the Rx data output rate, and the rate of

CLKOUT1 (clock used to latch output data) are the parameters

of interest for the receive path data. These parameters in addition

to the data bandwidth are related to CLKIN by decimation filters,

divide by two circuits, data multiplexer logic and retiming latches.

The Rx path timing can be broken into two separate relation-

ships: the ADC sample rate relative to the input clock, CLKIN

and the output data rate relative to CLKOUT1.

The ADCs sample rate relative to CLKIN is controlled by the

ADC Div2 register and the sample rate can be equal to or one half

of the input clock rate.

The output data relative to CLKOUT1 has many configurations

providing a flexible interface. The different options are shown in

Figure 8. Table Ia and Ib describe the setup required to obtain

the desired data timing. RxSync is available when the Rx data is

decimated and multiplexed to identify which channel data is

present at the output bus.

00: C = B

01: C = 2

10: C = 4

00: D = C

01: D = C/2

10: D = C/4

00: G = F

01: G = 2

10: G = 4

ADC SAMPLE RATE

(NOT TO EXCEED 64MHz)

DLL OUTPUT RATE

(NOT TO EXCEED 128MHz)

CLKOUT2

INPUT

Tx DATA RATE

TxDAC UPDATE RATE

EACH CHANNEL

(CANNOT EXCEED

DLL OUTPUT RATE)

DLL MULT

CLKOUT2 DIV

INTERP

0: E = D

1: E = 2

2 EDGES

F = E/2

DUAL CHANNEL

FACTOR

INPUT Tx DATA RATE

EACH CHANNEL

0: B = A

1: B = A/2

CLKIN

ADC DIV2

Figure 11. Dual Tx Timing Block Diagram, Alternative Operation

Tx DATA TIMING No. 1

fTx = CLKOUT2

Tx DATA TIMING No. 2

fTx = 2 CLKOUT2

CLKOUT2

Figure 12. Tx Timing Diagram

The Rx data (unless re-timed using the Rx Retime register) is

timed relative to the CLKOUT1 pin output. The Rx output data

can be decimated (halving the data rate) or both channels can be

multiplexed onto the channel A data bus (doubling the data rate).

Decimation enables oversampling while maintaining a slower

external data transfer rate and provides superior suppression of

out of band signals and noise. Multiplexing enables fewer digital

output bits to be used to transfer data from the Rx path to the

digital ASIC collecting the data.

When Mux Mode is enabled with an output data rate equal to

CLKOUT1 (Timing No. 3 in Figure 9) then the RxSync pin is

required to identify which channel’s output data is on the output

data bus. RxSync output is aligned with the output data, and by

default a logic low indicates data from Rx Channel B is currently

on the output data bus. If RxSync is logic high, then data from

Rx Channel A is currently on the output data bus. The Inv RxSync

The CLKOUT1 pin outputs a clock at the frequency of CLKIN or

CLKIN/2 depending on the voltage level applied to the CLKSEL

pin. If a logic low is applied to CLKSEL, CLKOUT1 will run

at half the CLKIN rate, if CLKSEL is set to logic high CLKOUT1

outputs a clock equal to CLKIN.

This timing flexibility along with the invert option for CLKOUT1,

controlled by the Inv 1 register allow for various methods of latch-

ing data from the Rx path to the digital ASIC, which will process

the data. These options are shown in Table Ia and Ib along with

a timing diagram in Figure 9. Not shown is the option to invert

CLKOUT1, controlled by the Inv 1 register. For this mode, relative

timing remains the same except the opposite edges of CLKOUT1

would be used.

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