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DS90CF366, DS90CF386

SNLS055J – NOVEMBER 1999 – REVISED MAY 2016

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Copyright © 1999–2016, Texas Instruments Incorporated

Timing Diagrams (continued)

(1)

The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O, and CMOS or LVCMOS I/O.

(2)

The 16 grayscale test pattern tests device power consumption for a typical LCD display pattern. The test pattern

approximates signal switching needed to produce groups of 16 vertical stripes across the display.

(3)

Figure 1 and Figure 3 show a falling edge data strobe (TxCLK IN/RxCLK OUT).

(4)

Recommended pin to signal mapping. Customer may choose to define differently.

Figure 2. Test Pattern, 16 Grayscale (DS90CF386)