FDC2114 datasheet(17/61 Pages) TI1

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FDC2212, FDC2214, FDC2112, FDC2114

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SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

Table 5. Settling Time Register Configuration

CHANNEL(1)

FIELD

CONVERSION TIME(2)

SETTLECOUNT_CH0, addr 0x10

CH0_SETTLECOUNT [15:0]

(CH0_SETTLECOUNT*16)/fREF0

SETTLECOUNT_CH1, addr 0x11

CH1_SETTLECOUNT [15:0]

(CH1_SETTLECOUNT*16)/fREF1

SETTLECOUNT_CH2, addr 0x12

CH2_SETTLECOUNT [15:0]

(CH2_SETTLECOUNT*16)/fREF2

SETTLECOUNT_CH3, addr 0x13

CH3_SETTLECOUNT [15:0]

(CH3_SETTLECOUNT*16)/fREF3

(1)

Channels 2 and 3 are available only in the FDC2114 and FDC2214.

(2)

fREFx is the reference frequency configured for the channel.

The SETTLECOUNT for any channel x must satisfy:

CHx_SETTLECOUNT > Vpk × fREFx × C × π

2 / (32 × IDRIVE

where

•

Vpk = Peak oscillation amplitude at the programmed IDRIVE setting

•

fREFx = Reference frequency for Channel x

•

C = sensor capacitance including parasitic PCB capacitance

•

IDRIVEX = setting programmed into the IDRIVE register in amps

(4)

Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of

6.08, program the register to 7 or higher).

The conversion time represents the number of reference clock cycles used to measure the sensor frequency.

It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:

tCx = (CHx_RCOUNT ˣ 16 + 4) /fREFx

(5)

The reference count value must be chosen to support the required number of effective bits (ENOB). For

example, if an ENOB of 13 bits is required, then a minimum conversion time of 213 = 8192 clock cycles is

required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.

Table 6. Conversion Time Configuration Registers, Channels 0 - 3(1)

CHANNEL

FIELD [ BIT(S) ]

CONVERSION TIME

RCOUNT_CH0, addr 0x08

CH0_RCOUNT [15:0]

(CH0_RCOUNT*16)/fREF0

RCOUNT_CH1, addr 0x09

CH1_RCOUNT [15:0]

(CH1_RCOUNT*16)/fREF1

RCOUNT_CH2, addr 0x0A

CH2_RCOUNT [15:0]

(CH2_RCOUNT*16)/fREF2

RCOUNT_CH3, addr 0x0B

CH3_RCOUNT [15:0]

(CH3_RCOUNT*16)/fREF3

(1)

Channels 2 and 3 are available only for FDC2114 and FDC2214.

The typical channel switch delay time between the end of conversion and the beginning of sensor activation of

the subsequent channel is:

Channel Switch Delay = 692 ns + 5 / fref

(6)

The deterministic conversion time of the FDC allows data polling at a fixed interval. For example, if the

programmed RCOUNT setting is 512 FREF cycles and SETTLECOUNT is 128 FREF cycles, then one conversion

takes 1.8ms (sensor-activation time) + 3.2ms (conversion time) + 0.75ms (channel-switch delay) = 16.75ms per

channel. If the FDC is configured for dual-channel operation by setting AUTOSCAN_EN = 1 and

RR_SEQUENCE = 00, then one full set of conversion results will be available from the data registers every

33.5ms.

A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register

description in Register Maps).

9.3.2.1 Gain and Offset (FDC2112, FDC2114 only)

The FDC2112 and FDC2114 have internal 16-bit data converters, but the standard conversion output word width

is only 12 bits; therefore only 12 of the 16 bits are available from the data registers. By default, the gain feature is

disabled and the DATA registers contain the 12 MSBs of the 16-bit word. However, it is possible to shift the data

output by up to 4 bits. Figure 15 illustrates the segment of the 16-bit sample that is reported for each possible

gain setting.

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