FDC2114 datasheet(20/61 Pages) TI1

20 / 61 page

FDC2212, FDC2214, FDC2112, FDC2114

SNOSCZ5A – JUNE 2015 – REVISED JUNE 2015

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Table 9. Current Drive Control Registers (continued)

CHANNEL(1)

FIELD [ BIT(S) ]

VALUE

DRIVE_CURRENT_CH2, addr 0x20 CH2_IDRIVE [15:11]

Drive current used during the settling and

conversion time for Ch. 2. Set such that

1.2V

≤ sensor oscillation amplitude (pk) ≤

1.8V

DRIVE_CURRENT_CH3, addr 0x21 CH3_IDRIVE [15:11]

Drive current used during the settling and

conversion time for Ch. 3 . Set such that

1.2V

≤ sensor oscillation amplitude (pk) ≤

1.8V

The CHx_IDRIVE field should be programmed such that the sensor oscillates at an amplitude between 1.2Vpk

(VSENSORMIN) and 1.8Vpk (VSENSORMAX). An IDRIVE value of 00000 corresponds to 16 µA, and IDRIVE = b11111

corresponds to 1563 µA.

A high sensor current drive mode can be enabled to drive sensor coils with > 1.5mA on channel 0, only in single

channel mode. This feature can be used when the sensor minimum recommended oscillation amplitude of 1.2V

cannot be achieved with the highest IDRIVE setting. Set the HIGH_CURRENT_DRV register bit to b1 to enable

this mode.

9.3.4 Device Status Registers

The registers listed in Table 10 may be used to read device status.

Table 10. Status Registers

CHANNEL(1)

FIELDS [ BIT(S) ]

VALUES

Refer to Register Maps section

12 fields are available that

All

STATUS, addr 0x18

for a description of the individual

contain various status bits [ 15:0 ]

status bits.

12 fields are available that are

Refer to Register Maps section

All

STATUS_CONFIG, addr 0x19

used to configure status reporting for a description of the individual

[ 15:0 ]

error configuration bits.

(1)

Channels 2 and 3 are available for FDC2114 and FDC2114 only.

See the STATUS and STATUS_CONFIG register description in the Register Map section. These registers can

be configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:

1. The error or status register must be unmasked by enabling the appropriate register bit in the

STATUS_CONFIG register

2. The INTB function must be enabled by setting CONFIG.INTB_DIS to 0

When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the

DATA_CHx register is read. Reading also de-asserts INTB.

Interrupts are cleared by one of the following events:

1. Entering Sleep Mode

2. Power-on reset (POR)

3. Device enters Shutdown Mode (SD is asserted)

4. S/W reset

5. I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS

along with the ERR_CHAN field and de-assert INTB

Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.

9.3.5 Input Deglitch Filter

The input deglitch filter suppresses EMI and ringing above the sensor frequency. It does not impact the

conversion result as long as its bandwidth is configured to be above the maximum sensor frequency. The input

deglitch filter can be configured in MUX_CONFIG.DEGLITCH register field as shown in Table 11. For optimal

performance, it is recommended to select the lowest setting that exceeds the sensor oscillation frequency. For

example, if the maximum sensor frequency is 2.0 MHz, choose MUX_CONFIG.DEGLITCH = b100 (3.3 MHz).

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