DP8430V datasheet(2/56 Pages) NSC

2 / 56 page

Table of Contents

10 INTRODUCTION

20 SIGNAL DESCRIPTIONS

21 Address RW and Programming Signals

22 DRAM Control Signals

23 Refresh Signals

24 Port A Access Signals

25 Port B Access Signals (DP8432V)

26 Common Dual Port Signals (DP8432V)

27 Power Signals and Capacitor Input

28 Clock Inputs

30 PROGRAMMING AND RESETTING

31 Reset

32 Programming Methods

321 Mode Load Only Programming

322 Chip Selected Access Programming

33 Internal Programming Modes

40 PORT A ACCESS MODES

41 Access Mode 0

42 Access Mode 1

43 Extending CAS with Either Access Mode

44 Read-Modify-Write Cycles with Either Access Mode

45 Additional Access Support Features

451 Address Latches and Column Increment

452 Address Pipelining

453 Delay CAS During Write Accesses

50 REFRESH OPTIONS

51 Refresh Control Modes

511 Automatic Internal Refresh

512 Externally Controlled Refresh

52 Refresh Cycle Types

521 Conventional Refresh

522 Staggered RefreshTM

523 Error Scrubbing Refresh

53 Extending Refresh

60 PORT A WAIT STATE SUPPORT

61 WAIT Type Output

62 DTACK Type Output

63 Dynamically Increasing the Number of Wait States

64 Guaranteeing RAS Low Time and RAS Precharge

Time

70 RAS AND CAS CONFIGURATION MODES

71 Byte Writing

72 Memory Interleaving

73 Address Pipelining

74 Error Scrubbing

75 PageBurst Mode

80 TEST MODE

90 DRAM CRITICAL TIMING PARAMETERS

91 Programmable Values of tRAH and tASC

92 Calculation of tRAH and tASC

100 DUAL ACCESSING (DP8432V)

101 Port B Access Mode

102 Port B Wait State Support

103 Common Port A and Port B Dual Port Functions

1031 GRANTB Output

1032 LOCK Input

110 ABSOLUTE MAXIMUM RATINGS

120 DC ELECTRICAL CHARACTERISTICS

130 AC TIMING PARAMETERS

140 DP8430V31V32V USER HINTS

DP8430V Datasheet(PDF) 2 Page - National Semiconductor (TI)

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