TAS5709APHPR datasheet(18/61 Pages) TI1

18 / 61 page

Overtemperature Protection

Undervoltage Protection (UVP) and Power-On

SSTIMER FUNCTIONALITY

CLOCK, AUTODETECTION, AND PLL

SERIAL DATA INTERFACE

PWM Section

TAS5709, TAS5709A

SLOS599A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com

The TAS5709 has an overtemperature-protection system. If the device junction temperature exceeds 150°C

(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the

high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5709 recovers automatically once the

temperature drops approximately 30°.

Reset (POR)

The UVP and POR circuits of the TAS5709 fully protect the device in any power-up/down and brownout situation.

While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully

operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and

AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD

pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being

asserted low.

The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when

exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current

source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the

desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is

shut down, the drivers are high-impedance and transition slowly down through a 3-k

Ω resistor, similarly

minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER pin capacitance.

Larger capacitors increase the start-up time, whereas capacitors smaller than 2.2 nF decrease the start-up time.

The SSTIMER pin should be left floating for BD modulation.

The TAS5709 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)

supports all the sample rates and MCLK rates that are defined in the clock control register.

The TAS5709 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×

fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section

uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the

internal clock (DCLK) running at 512 times the PWM switching frequency.

The DAP can autodetect and set the internal clock-control logic to the appropriate settings for all supported clock

rates as defined in the clock-control register.

TAS5709 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect

changes/errors. Once the system detects a clock change/error, it mutes the audio (through a single-step mute)

and then forces the PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the

system autodetects the new rate and reverts to normal operation. During this process, the default volume is

restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly

(also called soft unmute) as defined in volume register (0x0E).

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5709 DAP accepts serial data in

16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.

The TAS5709 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve high

power efficiency and high-performance digital-audio reproduction. The DAP uses a fourth-order noise shaper to

increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP

and outputs two BTL PWM audio output channels.

The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff

frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can

be enabled and disabled.

Submit Documentation Feedback

Product Folder Link(s): TAS5709 TAS5709A

TAS5709APHPR Datasheet(PDF) 18 Page - Texas Instruments

TAS5709APHPR Datasheet(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL