TAS5709APHPR datasheet(10/61 Pages) TI1

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AC Characteristics (BTL)

SERIAL AUDIO-PORT SLAVE MODE

TAS5709, TAS5709A

SLOS599A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com

PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,

fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating

conditions, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PVDD = 18 V, 10% THD, 1-kHz input

20.6

signal

PVDD = 18 V, 7% THD, 1-kHz input signal

19.5

PVDD = 12 V, 10% THD, 1-kHz input

9.4

Power output per channel

signal

PVDD = 12 V, 7% THD, 1-kHz input signal

8.9

PVDD = 8 V, 10% THD, 1-kHz input signal

4.1

PVDD = 8 V, 7% THD, 1-kHz input signal

3.8

PVDD = 18 V; PO = 1 W

0.06%

THD+N

Total harmonic distortion + noise

PVDD = 12 V; PO = 1 W

0.13%

PVDD = 8 V; PO = 1 W

0.2%

Output integrated noise (rms)

A-weighted

µV

PO = 0.25 W, f = 1kHz (BD Mode)

–82

Crosstalk

PO = 0.25 W, f = 1kHz (AD Mode)

–69

A-weighted, f = 1 kHz, maximum power at

SNR

Signal-to-noise ratio (1)

106

THD < 1%

(1)

SNR is calculated relative to 0-dBFS input level.

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

fSCLKIN

Frequency, SCLK 32 × fS, 48 × fS, 64 × fS

CL = 30 pF

1.024

12.288

MHz

tsu1

Setup time, LRCLK to SCLK rising edge

th1

Hold time, LRCLK from SCLK rising edge

tsu2

Setup time, SDIN to SCLK rising edge

th2

Hold time, SDIN from SCLK rising edge

LRCLK frequency

kHz

SCLK duty cycle

40%

50%

60%

LRCLK duty cycle

40%

50%

60%

SCLK

SCLK rising edges between LRCLK rising edges

edges

t(edge)

SCLK

LRCLK clock edge with respect to the falling edge of SCLK

–1/4

1/4

period

tr /

Rise/fall time for SCLK/LRCLK

tf(SCLK/LRCLK)

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