LP5550 datasheet(6/28 Pages) TI1

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LP5550

SNVS378G – OCTOBER 2005 – REVISED APRIL 2013

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LDO3 (Memory Retention Voltage) Characteristics

Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOUT Accuracy

Active state: Tracking VAVS

IOUT ≤ 50mA,VOUT = 1.2V,

-3%

1.2

3.0V

≤ VBAT1,2,SW ≤ 5.5V

Output Voltage Accuracy

Sleep state: Memory retention voltage

regulation

-3%

1.2

IOUT ≤ 5mA,VOUT = 1.2V,

3.0V

≤ VBAT1,2,SW ≤ 5.5V

VOFFSET

IOUT = 50 mA, VOUT = 0.6 V

Active State Buffer offset

(= VO3-VFB)

IOUT = 50 mA, VOUT = 1.2V

VOUT Range

Programmable Output Voltage

0µA

≤ IOUT ≤ 5mA,

0.6

1.2

1.35

Range (Sleep state)

Programming Resolution = 50mV

Active mode, IOUT = 10µA

(4)

µA

Quiescent Current

Sleep mode, IOUT = 10µA

(4)

µA

IOUT

Recommended Output Current,

3.0V

≤ VBAT1,2,SW ≤ 5.5V

Active state

Recommended Output Current,

3.0V

≤ VBAT1,2,SW ≤ 5.5V

Sleep state

Short Circuit Current Limit, Active

VOUT = 0V

230

state

Output Voltage Noise

10Hz

≤ f ≤ 100kHz, COUT = 1µF

0.158

mVRMS

PSRR

Power Supply Ripple Rejection

f = 217Hz, COUT = 1.0µF

Ratio

COUT

Output Capacitance

0.7

2.2

µF

0µA

≤ IOUT ≤ 5mA

Output Capacitor ESR

500

Ω

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

(4)

Quiescent current for LDO1, LDO2, and LDO3 do not include shared functional blocks such as the bandgap reference.

Switcher (Core Voltage) Characteristics

Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOUT Accuracy

IOUT = 150 mA, VOUT = 1.2V,

-3%

3.0V < VBAT1,2,SW <5.5V

Output Voltage

IOUT = 100-300 mA, VOUT = 1.2V,

-1.5%

1.5%

3.0V < VBAT1,2,SW <5.5V

VOUT Range

0mA

≤ IOUT ≤ 300mA,

Programmable Output Voltage

0.6

1.2

Range

Programming Resolution = 4.7mV

ΔVOUT

3.0V < VBAT1,2,SW <5.5V,

Line regulation

0.18

%/V

VOUT = 1.2V, IOUT = 10 mA

VBAT1,2,SW = 3.6V , VOUT = 1.2V,

Load regulation

0.0019

%/mA

IOUT = 100-300mA

Quiescent current consumption

IOUT = 0mA

µA

RDSON(P)

P-FET resistance

VBAT1,2,SW = VGS = 3.6V

360

690

Ω

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

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