LP5550 datasheet(7/28 Pages) TI1

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LP5550

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SNVS378G – OCTOBER 2005 – REVISED APRIL 2013

Switcher (Core Voltage) Characteristics (continued)

Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1)(2)(3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

RDSON(N)

N-FET resistance

VBAT1,2,SW = VGS = 3.6V

250

660

Ω

ILIM

Switch peak current limit

3.0V < VBAT1,2,SW <5.5V, Open Loop

350

620

750

fOSC

Internal oscillator frequency

PWM-mode

800

1000

1360

kHz

COUT

Output Capacitance

µF

0mA

≤ IOUT ≤ 300mA

Output Capacitor ESR

500

Ω

Inductor inductance

0uA

≤ IOUT ≤ 300mA

4.7 / 10

µH

RVFB

VFB pin resistance to ground

120

650

Ω

Logic and Control Inputs

Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

ENABLE, RESETN, SPWI, SCLK

Input Low Level

0.2

3.0V

≤ VBAT1 ≤ 5.5V

VIH

Input High Level

ENABLE, RESETN 3.0V

≤ VBAT1 ≤ 5.5V

VIH_PWI

Input High Level, PWI

SPWI, SCLK, 1.5V

≤VO2 ≤ 3.3V

VO2-0.2V

IIL

Logic Input Current

ENABLE, RESETN, 0V

≤ VBAT1 ≤ 5.5V

-5

µA

IIL_PWI

Logic Input Current, PWI

SPWI, SCLK, 1.5V

≤ VO2 ≤ 3.3V

-5

µA

RPD_PWI

Pull-down resistance for PWI

0.5

2.25

Ω

signals

TEN_LOW

ENABLE pulsed high - low - high from

100

SHUTDOWN state

Minimum low pulse width to enter

µsec

STARTUP state

ENABLE pulsed high - low - high from

SLEEP or ACTIVE state

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

Logic and Control Outputs

Unless otherwise noted, VBAT1,2,SW , RESETN, ENABLE = 3.6V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, -40 to

+125°C

(1) (2) (3)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VOL

Output low level

PWROK, SPWI, ISINK ≤ 1 mA

0.4

VOH

Output high level

PWROK, ISOURCE ≤ 1 mA

VBAT1-0.4V

VOH_PWI

Output high level, PWI

SPWI, ISOURCE ≤ 1 mA

VO2-0.4V

(1)

All voltages are with respect to the potential at the GND pin.

(2)

Min and Max limits are ensured by design, test, or statistical analysis. Typical (Typ) numbers are not specified, but do represent the

most likely norm. Unless otherwise specified, conditions for Typ specifications are: VIN = 3.6V and TA = 25°C control.

(3)

Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics

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