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DS1822 Datasheet(PDF) 14 Page - Dallas Semiconductor |
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DS1822 Datasheet(HTML) 14 Page - Dallas Semiconductor |
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14 / 20 page ![]() DS1822 14 of 20 1-WIRE SIGNALING The DS1822 uses a strict 1-Wire communication protocol to insure data integrity. Several signal types are defined by this protocol: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals, with the exception of the presence pulse, are initiated by the bus master. INITIALIZATION PROCEDURE: RESET AND PRESENCE PULSES All communication with the DS1822 begins with an initialization sequence that consists of a reset pulse from the master followed by a presence pulse from the DS1822. This is illustrated in Figure 13. When the DS1822 sends the presence pulse in response to the reset, it is indicating to the master that it is on the bus and ready to operate. During the initialization sequence the bus master transmits (TX) the reset pulse by pulling the 1-Wire bus low for a minimum of 480 ms. The bus master then releases the bus and goes into receive mode (RX). When the bus is released, the 5k pullup resistor pulls the 1-Wire bus high. When the DS1822 detects this rising edge, it waits 15 ms to 60ms and then transmits a presence pulse by pulling the 1-Wire bus low for 60 ms to 240ms. INITIALIZATION TIMING Figure 13 READ/WRITE TIME SLOTS The bus master writes data to the DS1822 during write time slots and reads data from the DS1822 during read time slots. One bit of data is transmitted over the 1-Wire bus per time slot. WRITE TIME SLOTS There are two types of write time slots: “Write 1” time slots and “Write 0” time slots. The bus master uses a Write 1 time slot to write a logic 1 to the DS1822 and a Write 0 time slot to write a logic 0 to the DS1822. All write time slots must be a minimum of 60 ms in duration with a minimum of a 1ms recovery time between individual write slots. Both types of write time slots are initiated by the master pulling the 1-Wire bus low (see Figure 14). To generate a Write 1 time slot, after pulling the 1-Wire bus low, the bus master must release the 1-Wire bus within 15 ms. When the bus is released, the 5k pullup resistor will pull the bus high. To generate a Write 0 time slot, after pulling the 1-Wire bus low, the bus master must continue to hold the bus low for the duration of the time slot (at least 60 ms). LINE TYPE LEGEND Bus master pulling low DS1822 pulling low Resistor pullup VPU GND 1-WIRE BUS 480 ms minimum 480 ms minimum DS1822 TX presence pulse 60-240 ms MASTER TX RESET PULSE MASTER RX DS1822 waits 15-60 ms |
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