EN

GND

V

IN

V

OUT

2

1

A

B

EN

GND

V

IN

V

OUT

2

1

A

B

TLV705, TLV705P

SBVS151E – DECEMBER 2010 – REVISED MAY 2015

www.ti.com

5 Pin Configuration and Functions

YFF, YFP Packages

YFM Package

4-Pin DSBGA

4-Pin PicoStar

Top View

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

GND

A1

—

Ground pin.

Enable pin.

EN

A2

I

Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown

mode, thus reducing operating current to 1

μA, nominal.

Regulated output voltage pin.

B1

O

A small 1-

μF ceramic capacitor is required to be placed from this pin to ground to assure stability.

See the Input and Output Capacitor Requirements section for more details.

Input pin.

B2

I

A small 1-

μF ceramic capacitor is recommended to be placed from this pin to ground for good transient

performance. See the Input and Output Capacitor Requirements section for more details.

4

Submit Documentation Feedback

Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: TLV705 TLV705P