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TLV705 Datasheet(PDF) 17 Page - Texas Instruments |
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TLV705 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 33 page ![]() CIN COUT GND VIN VOUT Represents via used for application-specific connections TLV705, TLV705P www.ti.com SBVS151E – DECEMBER 2010 – REVISED MAY 2015 10 Layout 10.1 Layout Guidelines Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), TI recommends designing the board with the input and output capacitors on opposite sides of the device. In addition, connect the ground connection for the output capacitor directly to the GND pin of the device. High ESR capacitors can degrade PSRR. 10.2 Layout Example Figure 31. Example PCB Layout 10.3 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the thermal dissipation. Refer to the section for thermal performance on the TLV705 evaluation module (EVM). The EVM is a 2-layer board with 2 ounces of copper per side. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 3: PD = (VIN – VOUT) × IOUT (3) 10.4 Power Dissipation and Junction Temperature Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TLV705 is designed to protect against overload conditions. Continuously running the TLV705 into thermal shutdown degrades device reliability. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TLV705 TLV705P |
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