RTL8139 datasheet(13/62 Pages) ETC

13 / 62 page

RTL8139C(L)

2002/01/10

Rev.1.4

6.2 Transmit Status Register

(TSD0-3)(Offset 0010h-001Fh, R/W)

The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139C(L) when the Transmit

Byte Count (bit12-0) in the corresponding Tx descriptor is written. It is not affected when software writes to these bits. These

registers are only permitted to write by double-word access. After a software reset, all bits except the OWN bit are reset to “0”.

Bit

R/W

Symbol

Description

CRS

Carrier Sense Lost: This bit is set to 1 when the carrier is lost during

transmission of a packet.

TABT

Transmit Abort: This bit is set to 1 if the transmission of a packet was

aborted. This bit is read only, writing to this bit is not affected.

OWC

Out of Window Collision: This bit is set to 1 if the RTL8139C(L)

encountered an "out of window" collision during the transmission of a

packet.

CDH

CD Heart Beat: The same as RTL8139(A/B).

This bit is cleared in the 100 Mbps mode.

27-24

NCC3-0

Number of Collision Count: Indicates the number of collisions

encountered during the transmission of a packet.

23-22

Reserved

21-16

R/W

ERTXTH5-0

Early Tx Threshold: Specifies the threshold level in the Tx FIFO to

begin the transmission. When the byte count of the data in the Tx FIFO

reaches this level, (or the FIFO contains at least one complete packet)

the RTL8139C(L) will transmit this packet.

000000 = 8 bytes

These fields count from 000001 to 111111 in unit of 32 bytes.

This threshold must be avoided from exceeding 2K byte.

TOK

Transmit OK: Set to 1 indicates that the transmission of a packet was

completed successfully and no transmit underrun occurs.

TUN

Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted

during the transmission of a packet. The RTL8139C(L) can re-transfer

data if the Tx FIFO underruns and can also transmit the packet to the

wire successfully even though the Tx FIFO underruns. That is, when

TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).

R/W

OWN

OWN: The RTL8139C(L) sets this bit to 1 when the Tx DMA

operation of this descriptor was completed. The driver must set this bit

to 0 when the Transmit Byte Count (bit0-12) is written. The default

value is 1.

12-0

R/W

SIZE

Descriptor Size: The total size in bytes of the data in this descriptor. If

the packet length is more than 1792 byte (0700h), the Tx queue will be

invalid, i.e. the next descriptor will be written only after the OWN bit of

that long packet's descriptor has been set.

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