automatically returns to track mode, and the next eight

clock cycles shift out the result on DOUT. The falling

edge of SCLK during the eighth bit of the result will

again cause the ADC to switch from track to hold mode

and begin the next conversion.

A minimum of 3.5µs in track mode is required for com-

plete acquisition.

In continuous ADC-only conversion mode, a new con-

trol word (START = 1) reconfigures the device.

Interrupted Communication Results

If CS transitions from low to high during the reception of

a control word, the MAX1102/MAX1103/MAX1104

enters its power-on reset state (full shutdown mode). If

CS is toggled while receiving DAC data, the input is

ignored and any received bits are discarded. In both

cases, once CS returns low, the device requires a new

control word before further conversions can occur. If

CS goes high while data is read from the device, DOUT

enters a high-impedance state, and the serial clock is

ignored. When CS returns low, the remaining bits of the

conversion result can be clocked out.

Applications Information

Power-On Reset

When power is first applied, the device enters full shut-

down mode and the DAC registers are reset to 0. To

wake up the device, the proper control word must be

written and 200µs allowed for the internal reference to

stablize. DAC data may be written to the device imme-

diately following the control word, but OUT will not finish

settling until the wake-up time has passed.

Power Sense

The MAX1102/MAX1103 provide a multiplexer which

power sensing capability to the system. When switch-

ing the input multiplexer, two control words must be

written before any conversion takes place. The first

control word changes the multiplexer state, and the

second starts the conversion.

Reference

The full-scale range of both the ADC and DAC is set by

the internal voltage reference. The MAX1102 provides a

+2.0V reference, the MAX1103 has a +4.0V reference,

ADC Transfer Function

Figure 9 depicts the ADC input/output transfer function.

Code transitions occur at the center of every LSB step.

Output coding is binary; with a 2.0V reference 1LSB =

and give a zero output code. Voltages greater than full

scale give an all ones output code.

Shutdown Modes

The MAX1102/MAX1103/MAX1104 feature four soft-

ware-selectable shutdown modes, helping to conserve

power by disabling any unused portion of the device.

Bits 0 through 2 of the control word select the device

shutdown mode (Table 1). Table 2 details the four

power modes with the corresponding supply current

and operating sections.

The ADC and DAC are individually controlled and can

be shutdown independently of each other. Bit 0 (E0)

controls the DAC, a logic “1” enables the DAC, a logic

“0” disables the DAC. Bit 1 (E1) controls the ADC, a

logic “1” enables the ADC, a logic “0” disables the

ADC. Either the ADC or DAC or both can be shutdown,

conserving power when one or both converters are not

in use. A fast wake-up time (3µs ADC, 10µs DAC)

allows the converters to be cycled in and out of shut-

down even during short duration idle times.

8-Bit CODECs

14

______________________________________________________________________________________

BIT

SUPPLY

CURRENT

OPERATING SECTIONS

E2

E1

E0

REF

ADC

DAC

00

0

1

µA

Off

Off

Off

10

0

18

µA

On

Off

Off

1

1

0

250

µA

On

On

Off

1

0

1

400

µA

On

Off

On

1

1

1

520

µAOn

On

On

Table 2. Operation Modes