PCM1794

SLES080B – MAY 2003 – REVISED NOVEMBER 2003

www.ti.com

22

IOUT–

Figure 25

Circuit

IOUT+

IOUTL– (Pin 26)

IOUTL+ (Pin 25)

OUT+

1

2

3

Balanced Out

IOUT–

Figure 25

Circuit

IOUT+

IOUTR– (Pin 18)

IOUTR+ (Pin 17)

OUT–

Figure 26. Measurement Circuit for Monaural Mode

APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE

DATA

24

23

22

21

20

19

18

17

16

15

5

6

7

8

9

10

11

12

13

14

PCM1794

BCK

SCK

DGND

VDD

MUTE

FMT0

FMT1

ZERO

RST

AGND2

IOUTR–

VCC1

VCOML

VCOMR

IREF

IOUTR+

AGND3R

AGND1

MONO

1

2

3

4

CHSL

DEM

LRCK

28

27

26

25

VCC2L

AGND3L

IOUTL–

IOUTL+

VCC2R

DATA

Analog

Output Stage

(See Figure 23)

WDCK

BCK

SCK

External

Filter

Device

VDD

Figure 27. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application