OPA643 datasheet(14/18 Pages) TI1

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OPA643

The total output noise voltage density can be computed as

the square root of the sum of all squared output noise voltage

contributors. Equation 1 shows the general form for the

output noise voltage using the terms shown in Figure 8.

Dividing this expression by the noise gain (NG = (1+RF/

RG)) will give the equivalent input referred spot noise

voltage at the noninverting input as shown in Equation 2.

Evaluating these two equations for the OPA643 component

values shown in Figure 1 will give a total output spot noise

voltage of 13.3nV/

√Hz and a total equivalent input spot

noise voltage of 2.7nV/

√Hz.

Narrowband communications systems are more commonly

concerned with the Noise Figure (NF) for the amplifier. The

total input referred voltage noise expression (Equation 2

above), may be used to calculate the noise figure. Equation

3 shows the noise figure expression using the EN of Equation

2 for the non-inverting configuration where the input

termination resistor RT has been set to match the 50Ω source

impedance (as shown in Figure 1).

Evaluating Equation 3 for the circuit of Figure 1 gives a

Noise Figure = 15.9dB. Input transformer coupling can be

used to reduce this noise figure. A broadband pulse

transformer can provide both a noiseless voltage gain and a

more optimum source impedance to minimize the noise

figure. Figure 9 shows an example built from the circuit of

Figure 1, in which the transformer turns ratio has been set to

the closest integer for minimum noise figure. This optimum

turns ratio is calculated by:

DC OFFSET CONTROL

The OPA643 provides excellent DC signal accuracy due to

the combination of high open-loop gain, high common-

mode rejection, high power supply rejection, low input

offset voltage and low bias current offset errors. The high

grade (B) version of any package type provides less than

1.5mV input offset voltage. To take full advantage of this

low input offset voltage, careful attention to input bias

current cancellation is also required. The high speed input

stage for the OPA643 has a relatively high input bias current

(19

µA typical into each input pin) but with a very close

match between the two input currents—typically 100nA

input offset current. The total output offset voltage may be

considerably reduced by matching the source resistances

which appear at the two inputs. For example, one way to

include bias current cancellation in the circuit of Figure 1

would be to insert a 55

Ω series resistor into the non-

inverting input after the 50

Ω terminating resistor, R

T. When

the 50

Ω source resistor is DC coupled, this will increase the

source resistance for the non-inverting input bias current to

Ω. Since this is now equal to the resistance appearing at

inverting input (RF || RG), the circuit will cancel the gains for

the bias currents to the output, leaving only the offset current

times the feedback resistor as a residual DC error term at the

output. Using a 402

Ω feedback resistor, this output error

will now be less than 3uA • 402

Ω = 1.2mV over the full

temperature range.

A fine scale output offset null, or DC operating point

adjustment, is often required. Numerous techniques are

available for introducing DC offset control into an op amp

circuit. Most of these techniques eventually reduce to setting

up a DC current through the feedback resistor. In selecting

an offset trim method, one key consideration is the impact

on the desired signal path frequency response. If the signal

path is intended to be non-inverting, the offset control is best

applied as an inverting summing signal to avoid interaction

with the signal source. If the signal path is intended to be

inverting, applying the offset control to the non-inverting

input may be considered—however, the DC offset voltage

on the summing junction will set up a DC current back into

the source which must be considered. Applying an offset

adjustment to the inverting op amp input can change the

noise gain and frequency response flatness. For a DC coupled

inverting amplifier, Figure 10 shows one example of an

offset adjustment technique that has minimal impact on the

signal frequency response. In this case, the DC offsetting

current is brought into the inverting input node through a

resistor which is much larger than the signal path resistors.

This will insure that the adjustment circuit has minimal

effect on the noise gain and hence the frequency response.

THERMAL ANALYSIS

The OPA643 will not require heatsinking under most

operating conditions. Maximum desired junction temperature

will set the maximum allowable internal power dissipation

as described below. In no case should the maximum junction

temperature be allowed to exceed 175

°C.

Eq. 1

O =

+ I

BN RS

()2 + 4kTR

()NG2 + I

BI R F

()2 + 4kTR

F NG

Eq. 2

N =

+ I

BN RS

()2 + 4kTR

S +

BI R F









4kTR

Eq. 3

= 10 log 2 +

kTRs













Eq. 4

FIGURE 9. Reduced Noise Figure Circuit.

OPT = Nearest Integer

N /I BN • RS /2

()









402

Ω

G = 15V/V [23.5dB]

Supply Decoupling

Not Shown

5.7dB

Noise Figure

S = 50Ω

1:6

OPA643

100

Ω

1.8k

Ω

Load

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