Rev: 1.12 7/2002

11/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS84018/32/36AT/B-180/166/150/100

Note:

There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be

unconnected and the chip will operate in the default states as specified in the above tables.

Burst Counter Sequences

Byte Write Truth Table

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

Mode Pin Functions

Mode Name

Pin

Name

State

Function

Burst Order Control

LBO

L

Linear Burst

H or NC

Interleaved Burst

Output Register Control

FT

L

Flow Through

H or NC

Pipeline

Power Down Control

ZZ

L or NC

Active

H

Function

GW

BW

Notes

Read

H

H

X

X

X

X

1

Read

H

L

HHHH

1

H

L

L

HHH

2, 3

HLHLH

H

2, 3

H

L

H

H

L

H

2, 3, 4

H

L

HHH

L

2, 3, 4

Write all bytes

H

LLLLL

2, 3, 4

Write all bytes

L

XXXX

X

Linear Burst Sequence

Note: The burst counter wraps to initial state on the 5th clock.

Note: The burst counter wraps to initial state on the 5th clock.

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

10

11

00

3rd address

10

11

00

01

4th address

11

00

01

10

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

00

01

10

11

2nd address

01

00

11

10

3rd address

10

11

00

01

4th address

11

10

01

00