GS84018 datasheet(17/31 Pages) GSI

17 / 31 page

Rev: 1.12 7/2002

17/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS84018/32/36AT/B-180/166/150/100

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.

3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ.

4. Device is deselected as defined by the Truth Table.

AC Test Conditions

Parameter

Conditions

Input high level

2.3 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

1.25 V

Output reference level

1.25 V

Output load

Fig. 1& 2

DC Electrical Characteristics

Parameter

Symbol

Test Conditions

Min

Max

Input Leakage Current

(except mode pins)

IIL

VIN = 0 to VDD

–1 uA

1uA

ZZ Input Current

IINZZ

VDD ≥ VIN ≥ VIH

≤ VIN ≤ VIH

–1 uA

1 uA

300 uA

Mode Pin Input Current

IINM

VDD ≥ VIN ≥ VIL

≤ VIN ≤ VIL

–300 uA

–1uA

1 uA

Output Leakage Current

IOL

Output Disable,

VOUT = 0 to VDD

–1 uA

1 uA

Output High Voltage

VOH

IOH = –4 mA, VDDQ = 2.375 V 1.7 V

Output High Voltage

VOH

IOH = –4 mA, VDDQ = 3.135 V 2.4 V

Output Low Voltage

VOL

IOL = 4 mA

0.4 V

VT = 1.25 V

Ω

30pF*

2.5 V

Output Load 1

Output Load 2

225

Ω

225

Ω

5pF*

* Distributed Test Jig Capacitance

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