P89C668 datasheet(13/89 Pages) PHILIPS

13 / 89 page

Philips Semiconductors

Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

VDD

OTHER DEVICE WITH

I2C INTERFACE

P89C66x

OTHER DEVICE WITH

I2C INTERFACE

P1.7/SDA

P1.6/SCL

SDA

SCL

I2C bus

SU01710

Figure 1. Typical I2C Bus Configuration

SCL

START

CONDITION

SDA

P/S

MSB

ACKNOWLEDGMENT

SIGNAL FROM RECEIVER

CLOCK LINE HELD LOW WHILE

INTERRUPTS ARE SERVICED

3–8

ACK

REPEATED IF MORE BYTES

ARE TRANSFERRED

ACKNOWLEDGMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

R/W

DIRECTION

BIT

STOP

CONDITION

REPEATED

START

CONDITION

SU00965

Figure 2. Data Transfer on the I2C Bus

SIO1 Implementation and Operation

Figure 3 shows how the on-chip I2C bus interface is implemented,

and the following text describes the individual blocks.

Input Filters and Output Stages

The input filters have I2C compatible input levels. If the input voltage

is less than 1.5 V, the input logic level is interpreted as 0; if the input

voltage is greater than 3.0 V, the input logic level is interpreted as 1.

Input signals are synchronized with the internal clock (fOSC/4), and

spikes shorter than three oscillator periods are filtered out.

The output stages consist of open drain transistors that can sink

3mA at VOUT < 0.4 V. These open drain outputs do not have

clamping diodes to VDD. Thus, if the device is connected to the I2C

bus and VDD is switched off, the I2C bus is not affected.

Address Register, S1ADR

This 8-bit special function register may be loaded with the 7-bit slave

address (7 most significant bits) to which SIO1 will respond when

programmed as a slave transmitter or receiver. The LSB (GC) is

used to enable general call address (00H) recognition.

Comparator

The comparator compares the received 7-bit slave address with its

own slave address (7 most significant bits in S1ADR). It also

compares the first received 8-bit byte with the general call address

(00H). If an equality is found, the appropriate status bits are set and

an interrupt is requested.

Shift Register, S1DAT

This 8-bit special function register contains a byte of serial data to

be transmitted or a byte which has just been received. Data in

S1DAT is always shifted from right to left; the first bit to be

transmitted is the MSB (bit 7) and, after a byte has been received,

the first bit of received data is located at the MSB of S1DAT. While

data is being shifted out, data on the bus is simultaneously being

shifted in; S1DAT always contains the last byte present on the bus.

Thus, in the event of lost arbitration, the transition from master

transmitter to slave receiver is made with the correct data in S1DAT.

P89C668 Datasheet(PDF) 13 Page - NXP Semiconductors

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