P89C668 datasheet(15/89 Pages) PHILIPS

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Philips Semiconductors

Product data

P89C660/P89C662/P89C664/

P89C668

80C51 8-bit Flash microcontroller family

16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM

2002 Oct 28

Arbitration and Synchronization Logic

In the Master Transmitter mode, the arbitration logic checks that

every transmitted logic 1 actually appears as a logic 1 on the I2C

bus. If another device on the bus overrules a logic 1 and pulls the

SDA line low, arbitration is lost, and SIO1 immediately changes from

master transmitter to slave receiver. SIO1 will continue to output

clock pulses (on SCL) until transmission of the current serial byte is

complete.

Arbitration may also be lost in the Master Receiver mode. Loss of

arbitration in this mode can only occur while SIO1 is returning a “not

acknowledge: (logic 1) to the bus. Arbitration is lost when another

device on the bus pulls this signal LOW. Since this can occur only at

the end of a serial byte, SIO1 generates no further clock pulses.

Figure 4 shows the arbitration procedure.

The synchronization logic will synchronize the serial clock generator

with the clock pulses on the SCL line from another device. If two or

more master devices generate clock pulses, the “mark” duration is

determined by the device that generates the shortest “marks,” and

the “space” duration is determined by the device that generates the

longest “spaces.” Figure 5 shows the synchronization procedure.

A slave may stretch the space duration to slow down the bus

master. The space duration may also be stretched for handshaking

purposes. This can be done after each bit or after a complete byte

transfer. SIO1 will stretch the SCL space duration after a byte has

been transmitted or received and the acknowledge bit has been

transferred. The serial interrupt flag (SI) is set, and the stretching

continues until the serial interrupt flag is cleared.

ACK

1. Another device transmits identical serial data.

SDA

SCL

(1)

(2)

(3)

2. Another device overrules a logic 1 (dotted line) transmitted by SIO1 (master) by pulling the SDA line low. Arbitration is

lost, and SIO1 enters the slave receiver mode.

3. SIO1 is in the slave receiver mode but still generates clock pulses until the current byte has been transmitted. SIO1 will

not generate clock pulses for the next byte. Data on SDA originates from the new master once it has won arbitration.

SU00967

Figure 4. Arbitration Procedure

(1)

SCL

(3)

(1)

SDA

MARK

DURATION

SPACE DURATION

(2)

1. Another service pulls the SCL line low before the SIO1 “mark” duration is complete. The serial clock generator is immediately

reset and commences with the “space” duration by pulling SCL low.

2. Another device still pulls the SCL line low after SIO1 releases SCL. The serial clock generator is forced into the wait state

until the SCL line is released.

3. The SCL line is released, and the serial clock generator commences with the mark duration.

SU00968

Figure 5. Serial Clock Synchronization

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