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GXM Datasheet(PDF) 221 Page - National Semiconductor (TI) |
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GXM Datasheet(HTML) 221 Page - National Semiconductor (TI) |
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221 / 244 page  Revision 3.1 221 www.national.com Instruction Set (Continued) SETL/SETNGE Set Byte on Less/Not Greater or Equal To Register/Memory 0F 9C [mod 000 r/m] --------- 1 1 h SETLE/SETNG Set Byte on Less or Equal/Not Greater To Register/Memory 0F 9E [mod 000 r/m] --------- 1 1 h SETNB/SETAE/SETNC Set Byte on Not Below/Above or Equal/Not Carry To Register/Memory 0F 93 [mod 000 r/m] --------- 1 1 h SETNBE/SETA Set Byte on Not Below or Equal/Above To Register/Memory 0F 97 [mod 000 r/m] --------- 1 1 h SETNE/SETNZ Set ByteonNot Equal/NotZero To Register/Memory 0F 95 [mod 000 r/m] --------- 1 1 h SETNL/SETGE Set Byte on Not Less/Greater or Equal To Register/Memory 0F 9D [mod 000 r/m] --------- 1 1 h SETNLE/SETG Set Byte on Not Less or Equal/Greater To Register/Memory 0F 9F [mod 000 r/m] --------- 1 1 h SETNO Set Byte on Not Overflow To Register/Memory 0F 91 [mod 000 r/m] --------- 1 1 h SETNP/SETPO Set ByteonNot Parity/ParityOdd To Register/Memory 0F 9B [mod 000 r/m] --------- 1 1 h SETNS Set Byte on Not Sign To Register/Memory 0F 99 [mod 000 r/m] --------- 1 1 h SETO Set Byte on Overflow To Register/Memory 0F 90 [mod 000 r/m] --------- 1 1 h SETP/SETPE Set Byte on Parity/Parity Even To Register/Memory 0F 9A [mod 000 r/m] --------- 1 1 h SETS Set Byte on Sign To Register/Memory 0F 98 [mod 000 r/m] --------- 1 1 h SGDT Store GDT Register To Register/Memory 0F 01 [mod 000 r/m] --------- 6 6 b,c h SIDT Store IDT Register To Register/Memory 0F 01 [mod 001 r/m] --------- 6 6 b,c h SLDT Store LDT Register To Register/Memory 0F 00 [mod 000 r/m] --------- 1 a h STR Store Task Register To Register/Memory 0F 00 [mod 001 r/m] --------- 3 a h SMSW Store Machine Status Word 0F 01 [mod 100 r/m] --------- 4 4 b,c h STOS Store String A [101w] --------- 2 2 b h SHL Shift Left Logical Register/Memory by 1 D [000w] [mod 100 r/m] x - - - x x u x x 1 1 b h Register/Memory by CL D [001w] [mod 100 r/m] u - - - x x u x x 2 2 Register/Memory by Immediate C [000w] [mod 100 r/m] # u - - - x x u x x 1 1 SHLD ShiftLeftDouble Register/Memory by Immediate 0F A4 [mod reg r/m] # u - - - x x u x x 3 3 b h Register/Memory by CL 0F A5 [mod reg r/m] 6 6 SHR Shift Right Logical Register/Memory by 1 D [000w] [mod 101 r/m] x - - - x x u x x 2 2 b h Register/Memory by CL D [001w] [mod 101 r/m] u - - - x x u x x 2 2 Register/Memory by Immediate C [000w] [mod 101 r/m] # u - - - x x u x x 2 2 SHRD Shift Right Double Register/Memory by Immediate 0F AC [mod reg r/m] # u - - - x x u x x 3 3 b h Register/Memory by CL 0F AD [mod reg r/m] 6 6 SMINT Software SMM Entry 0F 38 --------- 84 84 s s Table 9-27. Processor Core Instruction Set Summary (Continued) Instruction Opcode Flags Real Mode Prot’d Mode Real Mode Prot’d Mode OD I T S Z A P C FFFFFFFFF Clock Count (Reg/Cache Hit) Notes |
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